TPS65381 Watchdog Startup Issue with RM48

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Regards.

It is difficult to speculate the answer.

1. Can you publish the open/close window period of the TPS65381 and the code where you serve the watchdog in the MCU

2. SPI timings. What is the SPI frequency, and wdelay settings.

Other than that, I will consider it as a hardware fault.

Regards,

Haixiao

Haixiao,
Thanks for responding.
I have run this on multiple devices (multiple RM48's) and the behavior is the same on all, so I don't think this is a hardware fault.

Here is the SPI2 timing info:
SPI Clk: 500KHz
Chip Select Active to Transmit Start: 90.909ns
Transmit End to Chip Select Inactive: 90.909ns
Chip Select to ENA Timeout: 0.008ms
Transmit Finish to ENA Inactive Timeout: 0.009ms

Here is the setup I used for the open and close window configuration, which is copied from the FreeRTOS example

unsigned short OPEN_WINDOW_CONFIG = 40, CLOSE_WINDOW_CONFIG = 15;
ecmpWdgWindowConfig(OPEN_WINDOW_CONFIG, CLOSE_WINDOW_CONFIG);

Here is the code that serves the Watchdog:
(we are using SafeRTOS, which is based on FreeRTOS, e.g. xTaskDelay <=> vTaskDelay)

ecmpInit();
unsigned short OPEN_WINDOW_CONFIG = 40, CLOSE_WINDOW_CONFIG = 15;
ecmpWdgWindowConfig(OPEN_WINDOW_CONFIG, CLOSE_WINDOW_CONFIG);

( *( volatile unsigned int * )0xFFF7BC00U ) = 1;
( *( volatile unsigned int * )0xFFF7BC54U ) = 1<<7;

unsigned long TPSTaskCheck[4] = {0L};
volatile unsigned long *pTPSTaskCheck;
pTPSTaskCheck = &TPSTaskCheck[0];

TPSTaskCheck[2] = OPEN_WINDOW_CONFIG/2;
TPSTaskCheck[3] = OPEN_WINDOW_CONFIG/2+CLOSE_WINDOW_CONFIG/3;

for (;;)
{
  (*pTPSTaskCheck)++;
  short WdgFailCount = ecmpGetWdgFailCount();
  if (WdgFailCount == 0)
    {
    switch (*(pTPSTaskCheck+1))
      {
      case 0:
        if (ecmpEnableWdg())
        (*(pTPSTaskCheck+1))++;
        ecmpLockRegisters();
        break;
      case 1:
        if (ecmpLeaveDiagnosticState())
        (*(pTPSTaskCheck+1))++;
        break;
      default:
        break;
    }
  }
  ecmpSendWdgAnswer();
  ecmpSendWdgAnswer();
  ecmpSendWdgAnswer();
  xTaskDelay(*(pTPSTaskCheck+3));
  ecmpSendWdgAnswer();
  xTaskDelay(*(pTPSTaskCheck+2));
  if((*pTPSTaskCheck) & 0x1) ( *(volatile unsigned int *)0xFFF7BC60 ) = 1<<7;
  else (*( volatile unsigned int *)0xFFF7BC64 ) = 1<<7;
}

Thanks,

Bobby

Can you check WDELAY field in SPIFMT register? Please set it to 0x7F (a arbitary big number).

Please increase the SPI clock frequency to 1~5MHz.

Is there any other task in the system that block the CPU from serving the watchdog?

If possible, can you catch the wave form of SPI signal before/after you ask it to transfer from diagnostic to active mode.

Regards,

Haixiao

Thanks, Haixiao.  I increased the SPI clock to 1 MHz and changed the WDELAY to 127 (0x7F) and everything seems to work now.  I will do more testing to see where the frequency threshold is, below which we see the problem.  Is 127/0x7F a reasonable value for WDELAY?

Bobby

So now that I can go active and feed the watchdog reliably, the next problem is that when I attempt to attach a JTAG device for debugging or flashing, the JTAG debugger does a soft reset on the MCU.  Within 20 or 30 msec,  the 65381 resets the Hercules and repeatedly tries to reset it, causing multiple JTAG errors.  At hard reset, we have 600 msec to get into DIAGNOSTIC state and get the watchdog working, but at soft reset, it seems we have very little time before the 65381 issues a RESET and we get into an infinite reset loop.  Is there a way of configuring the 65381 to allow enough time for the Hercules to reset itself?

Haixiao,

Can you tell me how to configure the TPS65381 to prevent reset when the watchdog fails or at soft power-up?  I have NO_SAFE_TO bit set and SAFE_LOCK_THR = 0.  I can no longer debug because my MCU resets every time I try to debug or flash with JTAG.

Thanks,

Bobby