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T4C1294NCPDT EPI GP Register question

What is the difference between the EPADR / EPSZ and the ERADR / ERSZ (peripheral versus RAM) size and address.

My application involves a single FPGA connected to CPU via EPI in GP mode.

Another question:

Can I have reads and writes to/from the FPGA and somehow select either auto-increment address (for example accessing a linear sequence of addresses) or non-auto increment, for example accessing a FIFO port in FPGA?

Thanks

  • Hi David

    EPADR/EPSZ is used to access directly addressable devices, while ERADR/ERSZ is used for indirectly accessed memories in which address and data are sent separately

    Yes, you can have linear sequence and non-auto increment, but there is no bit to select that. As an example you can use NBRFIFO for linear spaces where address will be incremented and Block Read Path for non-auto increments..

    Amit