What is the difference between the EPADR / EPSZ and the ERADR / ERSZ (peripheral versus RAM) size and address.
My application involves a single FPGA connected to CPU via EPI in GP mode.
Another question:
Can I have reads and writes to/from the FPGA and somehow select either auto-increment address (for example accessing a linear sequence of addresses) or non-auto increment, for example accessing a FIFO port in FPGA?
Thanks