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Timing for DataFlash EEPROM

We are planning on using a TSM570x with Flash EEPROM.

The UserManual lists the following Timing values:

EEPROM Emulation (bank 7) Sector/Bank erase time (bank7)

-40°C to 125°C                               NOM: 0.08s    MAX: 8 s
0°C to 60°C, for first 25 cycles     NOM: 30ms   MAX: 100 ms


I have a few questions about these values.

1.) It is not clear to me, if these values are per Sector(4k) or per Bank(4k)?

2.) There is quite a significant difference from 30ms/80ms/100ms to 8s. Since we are operating in a very time critical environment, it would be a worst case for us if an erase cycle actually took "a few seconds". Is there any way to get more insight on this?

Best Regards,

Mathias Reinhard

  • The erase time is worst case for a single sector when doing sector erase, or the whole bank if doing bank erase. In bank erase all the sectors are being erased at the same time so the time of the bank erase is equal to the time to erase the slowest sector.

    Erase time degrades with the number of write erase cycles. Sometimes during erase traps (an extra electron or hole stuck in the oxide lattice) are formed in the erase oxide. These traps make the next erase harder. Some of the traps will anneal with time and high temperature. TI has very conservatively specified the maximum erase time to account for a worst case scenario of 90,000 cycles at high temperature (where traps form most easily), with no time between write erase cycles (no time for traps to anneal), then with 10,000 write erase cycles at cold temperature (where erase pulses are least effective). The 8 second specification was set so that even the slowest to erase device would finish in these extreme conditions.

    In summary, the erase time increases primarily with the number of write erase cycles, and secondarily as the temperature decreases. Also, the maximum erase time varies greatly between devices as they near the 100,000 write erase cycle limit.