Question about ECC Space initialization for TCRAM MINITGCR based Initialization

Hello:

We have received your post and we will come back to you soon.

Regards.

Hello Pashan,

  When you auto-initialize the TCRAM via the MINTGCR register, both the data and the ECC space will be initialized to 0x0 for the data and 0xC for the ECC. You don't need to enable ECC in the CP15 auxiliary control register and neither the ECC_DETECT_EN in the RAMCTRL register of the TCRAMW module for the initialization of the ECC space.

regards,

Charles

Hello Charles,

1> For TCMRAM, RAMCTRL Register ECC_DETECT_EN = any value, MINITGCR will always initialize ECC Space
2> For N2HET, HETPCR Register PARITY_ENA = any value, MINITGCR will always initialize N2HET RAM Parity Space
3> For MibADC, ADPARCR Register PARITY_ENA = any value, MINITGCR will always initialize MibADC RAM Parity Space
4> For HTU, HTU PCR Register PARITY_ENA = any value, MINITGCR will always initialize HTU RAM Parity Space [Control Packet RAM as well as WORKING Control Packet RAM]
5> For DCAN, DCANCTL Register PMD= any value, MINITGCR will always initialize DCAN RAM Parity Space
6> For MibSPI, UERRCTRL Register EDEN= any value, MINITGCR will always initialize MibSPI RAM Parity Space [Tx and Rx]
7> For VIM, PARCTLRegister PARENA= any value, MINITGCR will always initialize VIM RAM Parity Space

Can you please tell me whether all the above statements regarding MINITGCR based Peripheral RAM or TCMRAM or VIMRAM initialization are TRUE?

If not which one of the above statements are FALSE.

Thank you.
Regards
Pashan

Hello Pashan,

  I will get back to you as they may not be done in a consistent way. For example for VIM RAM, the PARENA needs to enabled in order for the parity bits to be initialized simultaneously.

regards,

Charles

Hello Pashan,

   Please find my answers below. As I said it is not done in a consistent manner across modules.

1> For TCMRAM, RAMCTRL Register ECC_DETECT_EN = any value, MINITGCR will always initialize ECC Space

True.

2> For N2HET, HETPCR Register PARITY_ENA = any value, MINITGCR will always initialize N2HET RAM Parity Space

False, you need to enable parity checking to also initialize the parity bits.

3> For MibADC, ADPARCR Register PARITY_ENA = any value, MINITGCR will always initialize MibADC RAM Parity Space

True. You don't need to enable parity checking to initialize the parity bits.

4> For HTU, HTU PCR Register PARITY_ENA = any value, MINITGCR will always initialize HTU RAM Parity Space [Control Packet RAM as well as WORKING Control Packet RAM]

False, you need to enable parity checking to also initialize the parity bits.

5> For DCAN, DCANCTL Register PMD= any value, MINITGCR will always initialize DCAN RAM Parity Space

False, you need to enable parity checking to also initialize the parity bits.

6> For MibSPI, UERRCTRL Register EDEN= any value, MINITGCR will always initialize MibSPI RAM Parity Space [Tx and Rx]

True. You don't need to enable parity checking to initialize the parity bits.

7> For VIM, PARCTLRegister PARENA= any value, MINITGCR will always initialize VIM RAM Parity Space.

False, you need to enable parity checking to also initialize the parity bits.

Can you please tell me whether all the above statements regarding MINITGCR based Peripheral RAM or TCMRAM or VIMRAM initialization are TRUE?

If not which one of the above statements are FALSE.

Hello Charles,

Forgot to ask about DMA :

8>For DMA, DMAPCR Register PARENA= any value, MINITGCR will always initialize DMA RAM Parity Space.

Please confirm whether the above statement is TRUE or FALSE.

Thank you for the all the previous answers.
Regards
Pashan