TM4C123

Hello Nabila

The maximum current driven by the GPIO is 25mA. You can drive it but you would be wearing down the IO faster. It would be advised to use a FET driven by the GPIO to drive the LED.

Also you may want to take into account the maximum current drive per side if more Pins are involved.

Both these parameters are mentioned in the Electrical Section of the datasheet under "Maximum Ratings" and "Recommended GPIO Pad Operating Conditions"

Regards

Amit Ashara

Hi Amit,

Thank you for the explanation.

Regards

Nabila

Seriously?  The IO wears down?

Randy

Hi Randy,

Operating it at Maximum Rated Operating Conditions stresses the structure, one of the multiple read's on the net

http://www.ewh.ieee.org/r6/scv/rl/articles/Does%20Silicon%20Wearout.pdf

Regards,

Amit

That article makes interesting reading! This has opened a can of worms!

So, silicon wears out.And the smaller the semiconductor feature size, the faster it wears out. If I read the graphs correctly, 65 nm semiconductor feature size only last 3 to 5 years! (Presumably depending on operating voltage ;-) ). I'd like my product to last more like 20 to 30 years.

So, there is a reliability versus performance trade off! I think I'd prefer reliability over performance.

Dear TI, can you please consider making your next microcontroller series using 130 nm technology, rather than 65 nm?

Hi Vito,

There are multiple reasons for geomteric's to be decided. 130nm while gives better reliability and lower leakage power, is not good from performance perspective. Higher Speed of operation is a bottleneck. Also the sixe of the chip will grow, making it take up valuable real estate on the board as well.

So really it is power v/s performance v/s reliability that a customer needs to look at as well when selecting a device.

Also the reliability factor is when you operate the device at the maximum operating limits for very long periods. If it is well below the life of the device is longer than the worst case.

Regards

Amit

Vito Casa said:

So, there is a reliability versus performance trade off! I think I'd prefer reliability over performance.

Dear TI, can you please consider making your next microcontroller series using 130 nm technology, rather than 65 nm?

 Hi Vito, small scale down to atomic size increase some quanta behavioural, increase radiation sensitivity but not long term failure if correctly understood. TIVA series is under development, has floating point unit on chip so it became difficult or expensive to produce on a 4 size larger scale.

 Remember defect probability is 4 time on 130nm than on 65, power raise with square of  so I prefer small scale, 65 nm is still bigger to atoms size to be reliable and not governated by quantuum.

 Current from pin is a different trouble, again area of silicon decrease, impedance of silicon decrease a lot but not the area needed to connect, power dissipated by single small transistor is a spot that need reradiate through, this is a trouble when a lot of port dissipate power at same time.

 If current drain from pin raise over 1mA is a good design rule to use external mosfet/bjt to also reduce noise on internal ADC if present.