HALCoGen Update for TMS570LS2*?

Mat,

We're assigning this thread to Prathap who's the lead for HalCoGen development, he can answer best.

In the meantime - have you reported the CAN clanger and the missing functionality to the forum.
If not it would be good to get the details so we can enter a ticket to track them.

Hi Mat,

Sorry for the inconvinence, I understand in Version 3.06.00 Software Quality of TMS570LS2* is not as mature as TMS570LS3* or RM4* Devices. We have planned to enhance TMS570LS2* by end of 1Q14.
But I can help you with any issues u might have.

Hi Pradeep,

We've got three main issues with the current code:

1). CAN Bus implementation:

   in reg_can.h, IF1CMD and IF2CMD are implemented as 32bit register accesses, which doesn't work: permanently sets the TX BUSY flag high when written to. Changing these to 8bit accesses corrects this problem.

2). LIN/SCI lacks /* USER CODE */ statement

   just to be awkward, we have one SCI and one LIN implementation. Although HALCoGen doesn't natively let us do this, trying to override the code is very difficult because the code is lacking any /*USER CODE...*/ statements between the functions. At the moment our only solution is to disable both LIN and SCI drivers and implement manually.

3). Lack of self-test / error reporting

   this is just a wish-list, but it'd be really good if there was support for testing the ECC/parity/self-test routines like the RM4 has inside the sys_selftest.c file. Tried modifying the RM4 version, but not suceeded!

If we could get hold of a beta version whcih corrects these issues, it'd be really good!

cheers

Mat

P.S. It'd also be really good to get a 'known issues list', so we don't blow time debugging existing problems!

Hi Mattew,

I do not have the list handy, I can definetly make one and give you end of this week. I will create a list comparing RM4 drivers to be more precise, just incase few functions can be ported by the user until official driver is released.

Hi Prathap,

Did you manage to get that list together?

Also found another problem whereby can.c blows away /*USER CODE BEGIN*/ entries when regenerating from HALCoGen

Hi Mathew,

I did a quick compare between the source codes and found following major difference between TM570LS20x and TMS570LS3x family.

- MISRA Compliance ( Majorly Typecasting related)
- GHS Support
- Register Naming mismatch Comparing TRM
- Safety SelfTest routines not implemented
- VIM Driver
- Stack handling for API's implemented in sys_core.asm ( Backing up R0 and restoring).
- Register Readback API for all Modules

Can you share the code snippet on the CAN issue that you are facing?

Note: I have raised the incompatibilty issue with high priority to HALCoGen team.

Thanks Prathap,

The major CAN issue (i.e. serious bug rather than nice to have) is that IF1CMD and IF2CMD are implemented as 32bit accesses, which doesn't work. You need to implement as seperate 8bit. Code below:

typedef volatile struct canBase
{
    uint32      CTL;          /**< 0x0000: Control Register                       */
    uint32      ES;           /**< 0x0004: Error and Status Register              */
    uint32      EERC;         /**< 0x0008: Error Counter Register                 */
    uint32      BTR;          /**< 0x000C: Bit Timing Register                    */
    uint32      INT;          /**< 0x0010: Interrupt Register                     */
    uint32      TEST;         /**< 0x0014: Test Register                          */
    uint32      rsvd1;        /**< 0x0018: Reserved                               */
    uint32      PERR;         /**< 0x001C: Parity/SECDED Error Code Register      */
    uint32      REL;          /**< 0x0020: Core Release Register                  */
    uint32      ECCDIAG;      /**< 0x0024: ECC Diagnostic Register                */
    uint32      ECCDIADSTAT;  /**< 0x0028: ECC Diagnostic Status Register         */
    uint32      rsvd2[21];    /**< 0x002C: Reserved                               */
    uint32      ABOTR;        /**< 0x0080: Auto Bus On Time Register              */
    uint32      TXRQX;        /**< 0x0084: Transmission Request X Register        */
    uint32      TXRQx[4U];    /**< 0x0088-0x0094: Transmission Request Registers  */
    uint32      NWDATX;       /**< 0x0098: New Data X Register                    */
    uint32      NWDATx[4U];   /**< 0x009C-0x00A8: New Data Registers              */
    uint32      INTPNDX;      /**< 0x00AC: Interrupt Pending X Register           */
    uint32      INTPNDx[4U];  /**< 0x00B0-0x00BC: Interrupt Pending Registers     */
    uint32      MSGVALX;      /**< 0x00C0: Message Valid X Register               */
    uint32      MSGVALx[4U];  /**< 0x00C4-0x00D0: Message Valid Registers         */
    uint32      rsvd3;        /**< 0x00D4: Reserved                               */
    uint32      INTMUXx[4U];  /**< 0x00D8-0x00E4: Interrupt Multiplexer Registers */
    uint32      rsvd4[6];     /**< 0x00E8: Reserved                               */
#if 0
    uint32      IF1CMD;       /**< 0x0100: IF1 Command Register                    */
#else
    uint8       rsvdIF1;      /**< 0x0100: IF1 Command Register, Reserved         */
    uint8       u8IF1CMD;     /**< 0x0100: IF1 Command Register, Command          */
    uint8       u8IF1STAT;    /**< 0x0100: IF1 Command Register, Status           */
    uint8       u8IF1NO;      /**< 0x0100: IF1 Command Register, Msg Number       */
#endif
    uint32      IF1MSK;       /**< 0x0104: IF1 Mask Register                      */
    uint32      IF1ARB;       /**< 0x0108: IF1 Arbitration Register               */
    uint32      IF1MCTL;      /**< 0x010C: IF1 Message Control Register           */
    uint8       IF1DATx[8U];  /**< 0x0110-0x0114: IF1 Data A and B Registers      */
    uint32      rsvd5[2];     /**< 0x0118: Reserved                               */
#if 0
    uint32      IF2CMD;       /**< 0x0120: IF2 Command Register                    */
#else
    uint8       rsvdIF2;
    uint8       u8IF2CMD;
    uint8       u8IF2STAT;
    uint8       u8IF2NO;
#endif
    uint32      IF2MSK;       /**< 0x0124: IF2 Mask Register                      */
    uint32      IF2ARB;       /**< 0x0128: IF2 Arbitration Register               */
    uint32      IF2MCTL;      /**< 0x012C: IF2 Message Control Register           */
    uint8       IF2DATx[8U];  /**< 0x0130-0x0134: IF2 Data A and B Registers      */
    uint32      rsvd6[2];     /**< 0x0138: Reserved                               */
    uint32      IF3OBS;       /**< 0x0140: IF3 Observation Register               */
    uint32      IF3MSK;       /**< 0x0144: IF3 Mask Register                      */
    uint32      IF3ARB;       /**< 0x0148: IF3 Arbitration Register               */
    uint32      IF3MCTL;      /**< 0x014C: IF3 Message Control Register           */
    uint8       IF3DATx[8U];  /**< 0x0150-0x0154: IF3 Data A and B Registers      */
    uint32      rsvd7[2];     /**< 0x0158: Reserved                               */
    uint32      IF3UEy[4U];   /**< 0x0160-0x016C: IF3 Update Enable Registers     */
    uint32      rsvd8[28];    /**< 0x0170: Reserved                               */
    uint32      TIOC;         /**< 0x01E0: TX IO Control Register                 */
    uint32      RIOC;         /**< 0x01E4: RX IO Control Register                 */
} canBASE_t;