Other Parts Discussed in Thread: TM4C123GH6PGE
I have Tiva board TM4C123G Development Board with OLED Display. With reference to that, I have some technical queries pertaining to Tiva controller TM4C123GH6PGE.
In our system, we have asynchronous communication over RS485 alongwith Display and Keypad modules. Below are the queries that seems to be critical in our design phase.
Queries:
1. UART - We can set trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 on Receive FIFO to generate interrupt. Suppose, we set it to 1/8 level, so after every 2 bytes, interrupt is triggered. Another trigger for interrupt is Receive Timeout which is explained in Section 14.3.9 Interupts of UART.
The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data is received over a 32-bit period when the HSE bit is clear or over a 64-bit period when the HSE bit
is set. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data (or by reading the holding register), or when a 1 is written to the corresponding bit in the
UARTICR register.
32-bit period will depend on the UART Baud Rate or System Clock? Is there any default period defined? We have seen /uart_echo example provided with Tiva.
2. GPIO – GPIO Port Change Interrupt can be triggered at Edge or Level. In datasheet, for Level triggered interrupt, it is written
For a level-sensitive interrupt, the external source must hold the level constant for the interrupt to be recognized by the controller….For a GPIO level-detect interrupt, the interrupt signal generating the interrupt must be held until serviced.
Until what time should the Level be maintained constant? Please provide an example code for this.
Regards and thanks,
blueshift
