• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Subscribers 32 subscribers
  • Views 1842 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

EMIF async read page mode timings

Stefan Steinmann
Intellectual 410 points


Hi,

I am using a LS3137 device with an external NOR flash connected to the asynchronous CS3 of the EMIF.

As I would like to use the page mode, I have a question regarding the EMIF timings.

In the datasheet in table "4-28", item "12" is the time stated (30ns) how long the data needs to be valid before nOE goes high. From my understanding this is more the time how long the data needs to be valid before the CPU samples the data lines.

So how does it work if the async page read mode is used? In this case the nOE line stays low for the page size. Does this time need to be considered or not? Unfortunately in the data sheet there is no timing stated regarding the page mode. Only the TRM considers the page mode and states in the register description for the "pg_delay" (1)  that the minimal value has to be 2x EMIF_CLK cycles. But what about (2) ?

thanks,

Stefan

  • 0
    TI__Guru 68950 points

    Stefan,

    One of the guys on our team started looking into this already;  as we've had multiple queiries.
    I'm assigning your post to him.

  • 0 in reply to Anthony F. Seely
    Intellectual 410 points

    Hi,

    is there any update / new information on this point?

    thanks,

    Stefan

  • 0 in reply to Stefan Steinmann
    TI__Expert 4225 points

    Hi Stefan,

    The async page mode timing is not the data sheet and the number in TRM is not correct.  We will remove it from TRM.  

    In async read page mode, the user needs to program the PMCR register for nCS_PG_DEL.  This value is defined as the time for address change to read data valid.  

    I hope this helps.

  • 0 in reply to Henry Nguyen
    Intellectual 410 points

    Hi Henry,

    thanks for the feedback. So far this was clear. The initial question was:

    1) what is the minimum time for nCS_PG_DEL?

    2) is the page mode also affected of the EMIF design issue which lead to the long 30ns setup time (no. 12 of table 4-28 in spns162b?

    If YES, nCS_PG_DEL = 30ns + address change to read data valid

    br

    Stefan

  • 0 in reply to Stefan Steinmann
    Intellectual 410 points

    Is my question still under investigation?

    I would need an answer on my question.

  • 0 in reply to Stefan Steinmann
    TI__Expert 4225 points

    Hi Stefan,

    I am sorry for the late response.

    According to the EMIF TRM, the minimum page delay can be 1 EMIF clock which is 0 value is programmed (always minus 1).

    However, you can not just program any arbitrary number.  Let's take a look at the NOR flash read page mode from Micron for example:

     https://www.micron.com/~/media/Documents/Products/Technical%20Note/NOR%20Flash/tn1320_m29w320d_async_page_mode_read.pdf

    In this Micron flash case, the AVQV1 is defined as 20-25 ns min to max condition.  Please note that AVQV1 is for subsequent data phase (which is page read phase), not the first data phase.

    Assume our internal EMIF CLK is running at 50 MHz, then, the way to calculate the page delay in term of cycle is:

    Period * frequency = 25 ns * 50 MHz/1000 = 1.25 cycles which is rounded up to 2 cycles.  

    Thus, you need to program as number cycles -1 = 2-1=1 clock cycle.

    In this case, the EMIF controller will "latch" the data on the second rising edge of the clock after the address changes.  The number of clock will changes the the EMIF internal clock frequency changes.

    I hope this helps.  

  • 0 in reply to Henry Nguyen
    TI__Expert 4225 points

    Hi Stefan,

    For your second question, no this parameter has nothing to do with it.  The parameter you mentioned is for last data phase of the async interface.

    Hope this helps.

  • 0 in reply to Henry Nguyen
    Intellectual 410 points

    Henry Nguyen said:

    Hi Stefan,

    For your second question, no this parameter has nothing to do with it.  The parameter you mentioned is for last data phase of the async interface.

    Hope this helps.

    Hi Henry,
    thanks for your answer. One last question remains:
    Your mentioned "last data phase" could be interpreted to happen also for the last WORD read in page mode.
    After the EMIF Address change, this last WORD is valid after tAVQV1(25ns).
    As this is the last word, the EMIF nOE would go to high after 40ns from the last address change.
    So the data was valid only for 40-25 = 15ns.
    Is this really not violating parameter "12"? Is "12" only valid for normal reads?
  • 0 in reply to Stefan Steinmann
    TI__Expert 4225 points

    Hi Stefan,

    By last data phase, i meant last word of the page read.

    I already checked with the EMIF designer that the last word also has to follow the page read requirement.

    The parameter 12 is only for normal read.

    Hope this helps.