ADC total sampling time

matteo lucarelli

Other Parts Discussed in Thread: HALCOGEN

Hi,

I'm working with RM48HDK.I'm using the RTI to trigger ADC in single mode. The tTotal shown by halcogen is not in agreement with the time between trigger (if I set the higher tTime which should be compatible with the time between the trigger the ADC loses a lot of data)

Using the documented formula 13*cycleTime + tSample (as shown by Halcogen as tTotal) does not work with high trigger frequency (~1MHz).

I need to optimize the sample time to maximize signal to noise ratio. How can I calculate the total time required for a single ADC?

Thank you

over 11 years ago

0 Sunil Oak over 11 years ago

TI__Mastermind 49120 points

Hi Matteo,

There are 4 VCLK cycles from the end of conversion of one channel to the start of sampling of the next channel selected for conversion in the same group.

If a separate conversion group is triggered while a conversion is in progress, then there are 6 VCLK cycles from the end of conversion of the current channel to the start of sampling of the channel selected in the next group.

We will include these timings in the next update to our docs.

Regards, Sunil

0 matteo lucarelli over 11 years ago in reply to Sunil Oak

Genius 3265 points

What if I'm using just one channel?

0 Sunil Oak over 11 years ago in reply to matteo lucarelli

TI__Mastermind 49120 points

There are 5 VCLK cycles from a software trigger (write to ADGxSEL) to start of sampling.

There are 6 VCLK cycles from an event trigger (rising/falling edge) to start of sampling.

Regards, Sunil

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ADC total sampling time