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RM48 HDK ECC test

Andrew Hartnett
Intellectual 890 points
Other Parts Discussed in Thread: HALCOGEN

Hello,

I'm trying to write some code to check RAM during a test we have coming up soon. I basically fill up the RAM at the beginning of the code and sit in a loop reading it back making sure it matches what was written.

I'd like to enable ECC for the RAM to keep track of single bit errors, fixes, and such. However reading this post http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/304025.aspx gives me the impression that if there were a double bit error that the program halts - which is not my desired functionality. 

I remember reading/hearing that there's a register that keeps track of how many single bit errors have occurred - but I am having trouble finding the details of it in the datasheet (I'm looking at spns174a). 

Also, is there a way to prevent the code from aborting if there is a double bit error? How can I control what happens if the processor discovers there's any error?

Thanks for the help.

  • 0
    TI__Guru**** 191886 points

    Hello Andrew,

      In the RM48x TRM SPNU503B page 304-305 you will find the single bit error threshold and occurance registers inside the TCM (Tightly Coupled Memory) module. You can setup the threshold value before which the number of single bit errors detected can generate an interrupt to the CPU. This feature is for the system level to profile the error behavior. Note that error detection and correction is done inside the CPU. You must enable ECC in the CPU's Auxiliary Control Register. You must also enable the X bit in the Performance Monitor Control Register in the CPU in order for the TCM Wrapper to count the number of single it error occurances.

      Single bit errors is correctable and will not result in abort unless you disable the correction in bit3 of the Secondary Auxillary Control Register in the CPU. When the ECC is enabled and detected a double bit error, it will abort. The abort can be prefetch abort for instruction fetch or data abort for data read. A double bit error is serious enough that there is no mechanism to disable the CPU from an abort unless you disable the ECC checking. HalCoGen has an example code for handling a double bit error. Please check dabort.asm file.

    regards,

    Charles

  • 0 in reply to Charles Tsai
    Intellectual 890 points

    I am running HALCoGen 03.06.00 and don't see any example code for handling a double bit error. Do you just mean that dabort.asm is the example?

    An abort is different than a system reset or halt through, right? If I just want to acknowledge that there's been a double bit error but want to continue running my program normally otherwise so I can get an idea of how frequently it happens in the environment I'm running in there's no way to test that? 

    Thanks

  • 0 in reply to Andrew Hartnett
    TI__Guru**** 191886 points

    Hello Andrew,

      HalCoGen will generate the dabort.asm file. I'm also attaching here.8838.dabort.asm

      Abort is not halting or resetting the CPU. Abort is a form of exception similar to interrupts but of higher priority. The program will resume it normal execution once it exits the abort routine. In the data abort routine, you will need to find out the cause of the double bit error and try to fix the problem. When you exit the data abort routine the return instruction will take you back to the same instruction which caused the original double error error. So if you don't fix the problem in the abort routine then it will be in a loop for abort.

    regards,

    Charles