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RM48 and eMMC 4.3 and Above

Sean Giuricin
Prodigy 100 points

Hi ,

I am trying to interface eMMC to the RM48. However since 4.3 of the eMMC standard the SPI support has been removed which leaves SD/MMC/SDIO as the only connectivity option. eMMC or Managed NAND are our preferred technologies

As far as I’m aware the RM48 does not have an SDIO module.

Are there any other options for me for connecting the eMMC to the RM48?

 

An SPI to SDIO Module?

NAND Flash connected to the EMIF?

SPI NAND Flash?

Thanks

Sean

  • 0
    TI__Guru 68920 points

    Hi Sean,

    I only skimmed the eMMC spec and don't have the bandwidth to go deep into it at the moment.

    But, it look like while SPI mode is gone, they still have a 1-pin serial mode.  It *looks* like the main difference is that the data pin is bidirectional in this mode. 

    I wonder if you couldn't make our MibSPIP handle this type of memory simply by tying the SOMI & SIMO pins together and managing the 3-stating of the SIMO pins during the part of the protocol that requires the eMMC device to send data back to the micro.   And our MibSPIP on the RM48 actually does have a 4-pin parallel mode so you could probably get a decent data rate.

    The main concern I'd have is if I saw in the eMMC spec that the clock had to be provided as a free-running clock.  With our MibSPI the clock will be inactive between transfers so it will be bursty.   As long as the eMMC devices can handle this then it might be largely an exercise in writing software to emulate an eMMC interface using the MibSPIP.  

    NAND flash on the EMIF might work but beware that we have an errata about the generation of extra cycles with the chip select active but no data masks.  This is an artifact of the x64 internal bussing connecting to a x32 memory interface.  You might need to either change the mode of the MPU or add some glue logic to qualify the chip select with the data strobes if you decide to go down this path.

    SPI flash in general should work well with the MibSPIP.  I haven't kept current as to whether most SPI flash is NOR or NAND though.   Generally NOR is a lot easier to use if you can afford it;  since NAND usually requires error correction which you might need to do in software if the memory doesn't abstract it from you. 

     

  • 0 in reply to Anthony F. Seely
    Prodigy 100 points

    Thanks Anthony,

    I also had a similar idea of gating the SIMO output using a tri-state buffer while connecting the 1bit data line to the SOMI pin.

    I think this is the solution I will attempt, however I was hoping to for a more elegant solution.

    I'd love to hear from somebody why has attempted this

     

     

    Cheers

    Sean

  • 0 in reply to Sean Giuricin
    Prodigy 100 points

    I had a further look over the eMMC protocol and you're right about the running clock. Bit bashing this seems like not the right way to go about it.

    Doing some further digging I have found a device (SDIO101A) offered by NXP that I believe will allow me to connect my eMMC to the EMIF port. Does TI offer any such products?