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Memory guarding on TMS570

Andy Worsley
Intellectual 640 points

Hi,

I have been asked if the TMS570 has a facility to do memory guarding. They seem to think I'm the expert on this micro. Lord help me!

My understanding of what they want is if there is low level code in one area and customer application code in another is there a mechanism for preventing access of application to the low level code, and vice versa, and would this generate an exception?

Any help you can give me here would be appreciated.

Thanks

Andy

  • 0
    TI__Mastermind 23000 points

    Hi Andy,

    Please take a look at the Memory Protection Unit (MPU) which is integrated into the Cortex R4 CPU.  You can define a number of regions with different access permissions, generally 12 on the Hercules devices.  If a CPU access is attempted which violates the defined access permissions, then a prefetch abort or data abort will be generated depending on whether the fault was on instruction or data access respectively.

    Best Regards,

    Karl