Hello Support,
In the TRM I see the following statement :
"The serial implementation of LFSR has a limitation that, it requires n clock cycles to calculate the CRC values for an n-bit data stream."
I am operating in FULL_CPU Mode of CRC Engine.
Using STRD Instruction I am writing to PSA_SEGREGL1 [Offset 0x60 of CRC Address Frame].
Then I am reading from PSA_SIGREGL1 using LDRD Instruction.
Do I have to put 64-Clock cycle delay before LDRD Instruction because CRC Engine takes 64-Clock Cycle to calculate the final CRC Value for every STRD Instruction?
If not, then some explanation will be beneficial for me to understand better the behaviour of CRC Engine. Because it is a LFSR I am assuming it takes 64-Clock Cycle to pass all the input DATA Strem bits every time STRD instruction executes.
Or, is it that there is an inherent WAIT STATE of 64-Clock Cycle is always there when CPU access CRC Address Frame?
Thank you.
Regards
Pashan
