Some questions about N2HET timing

Hi Matteo,

matteo lucarelli said:

From the TRM (table 20-5) the hr prescale divider rage is 1 to 64 but in the HalCoGen (v03.08.00) input field higher values are accepted. Why?

I just tried this and don't see the same thing.  The input in my installation is the frequency in MHz and the divider is calculated as an output.  If I ask for 1MHz HR Clock I get /63 and an actual value of ~1.5Mhz...

matteo lucarelli said:

The default value for VCLK2 (for RM48HDK) is 100MHz. Raising it to its maximum (200MHz) has some negative side effect?

VCLK2 is limited to 100MHz or so depending on the part #.   For RM48L952 you can go to 110MHz.

matteo lucarelli said:

Assuming (for example) VCLCK=160Mhz, hr=1, lr=8 the HET program has 8 time slots for its execution and the maximum detactable external frequency is 10MHz with 50% duty cycle. I'm I right? Do I understand correclty the Input Timing specification (5.4.3 of the Datasheet)?

The loop consists of 8 time slots.  You need to branch back to the address 0 though by the last time slot or an overflow flag will be set, so actually only 7 slots are useable.

Regarding detection of an input,  let's rephrase the question to be specific to PCNT and WCAP where you are making a timing measurement of the input pin.  

There are two groups of pins, some with an enhanced measurement capabilty (I think 6 total) and the remainder with normal capability.    Pins with the 'normal' capability as listed in the table 5-13 (Having 'No' under Enhanced Pulse Capture) must meet the input constraints of table 5-11.   In a nutshell, the measurement only works when there is a maximum of one edge on a pin during a given loop resolution period.     This means that both the high and the low pulse widths need to be > 1 loop resolution period (we specify by 2ns) and from this you get the 50% duty cycle input (best case) frequency limit of 2 loop resolution periods (that is 16 HR clocks + 2ns in your example).

The enhanced pins can measure one of the pulse periods (either high or low) down to 2 HR clocks but the period is still limited to 2 loop resolution periods.    So the frequency of your fastest input is still the same, but the 50% duty cycle restriction is relaxed because now instead of 8 cycles high and 8 cycles low you could measure 2 cycles high / 14 cycles low or 14 cycles high / 2 cycles low.. at this fastest input frequency.

Back to my comment about rephrasing your question.  You originally asked about 'detection'.
What I answered was 'detected and measured correctly.   There's a continuum: 

  o slower than spec: will be detected and measured correctly.

  o faster than spec:  probably detected, but may or may not be measured correctly

  o much faster than spec:  may or may not be detected.  may or may not be measured correctly if detected.

The only answer you can rely on is the first, where you are meeting the spec. 

If you go faster than the spec, the HET may still respond however.   So if you need to get rid of that response you either need to enforce the minimum pulse width externally OR turn on the input filter feature of the HET.

Hi Antony,

about the Halcogen tab you're right. My mistake (don't know why).

About the frequency your answer is clear (so my example is right: if I want to measure edges the external pulse period must be longer than 2 loops. Right?).

About the clocks: the table for RM48L950 (the one in the HDK) is different:

And only 5 frequency fange are reported. My questions:

1. For VCLKA3 48Mhz are reported as maximum but in the Halcogen i can set it to 200. Even 200 is the default value. Same for VLCLKA4. Why?
2. RTICLK is not present in the HalCoGen tabs. Where is it used?
3. For all the others clock there are not reported ranges. In the HalCoGen GCM table all can be set to 200MHz. Is that right?
4. The VCLK3 (the HET one) is not set to 200MHz by default.  There may be some problem in setting it to 200MHz? (Same for the others: there are some brawbacks in driving all to the max?)

Here my HalCoGen GCM tab with default values for a new TMDXRM48HDK project:

Antony,

so, meanwhile a complete datasheet on maximum frequency is not available, is safer is not to increase any value in HalCoGen GCM table?

About RTI my doubt was raised by its absence in the "clock tree" table, but obviusly RTICLK is used by RTI, so its clear.

Nevertheless I don't understand why, for example, for VCLKA4 my, uncomplete, table report a maximum frequency of 50MHz while the default value in HalCoGen is 100MHz. Is this safe?

Hope complete information about maximum clock freq will be available soon. If are listed somewhere else please inform me.

Ok. Information are enough for the moment and I can consider the thread closed.

I hope a corrected version of the datasheet will be out soon.

Let me know.

Matteo