configuring hardware timer

Hi Nabila

Is this TM4C123 or TM4C129 device?

Regards

Amit

It's tm4c123. You can explain for both. It will be good for me.:)

Regards

N

Hi Nabila

On TM4C123 there is no configuration required for enabling or disabling DMA from timers. The DMA Request is asserted when the corresponding RIS bit for the mode of operation is set. As an example if the Timer is being used for Compare Match event, then when the number of input edges match the programmed value the GPTMRIS.CAMRIS is set and also the DMA Request is sent to the DMA Controller.

The only configuration that is needed is that of the UDMA. The UDMA Has to be enabled, the control table base address set, the channel source-destination address pointers set, transfer size, arbitration size, transfer type also set and the UDMA Channel Enabled.

On TM4C129, there is a GPTDMAEV register where the source of the DMA Request can be masked or unmasked, but everything else remains the same.

Regards

Amit

Thanks Amit. What is fifo trigger level in page 890

FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8

Thanks

Hello Nabila,

This is for the UART I believe? The UART has a 16x8 deep FIFO. The trigger level means at what level of the FIFO does the Interrupt TXRIS or RXRIS gets triggered. Doing the maths it would be 1,2,4,6 and 7 as the levels.

in the RX direction a trigger level of 1/2 would mean that when there is 4 bytes of data a RXRIS interrupt will be asserted.

In the TX direction a trigger level of 1/2 would mean that when there is space for 4 bytes to be written a TXRIS will be asserted

Regards

Amit