DIVSCLK Bug found for TIVA C series pinmux utility

Hi, Guys,

I'm using the same code to enable the DIVSCLK on PQ4 to clock a SPI motor driver chip. I never get it work with the GPIOPadConfigSet() function because it will lock the Tiva C MCU on EK-TM4C1294XL board. if I comment out GPIOPadConfigSet() function, the code seems works but no waves on the PQ4.

Any one has any clue on this issue?

Thanks in advance.

Ron

Hello All,

Enabling the Pad is not sufficient to get the clock out. The following API with the source of the clock and the divided down value is also needed

SysCtlClockOutConfig

Regards

Amit

Hi, Amit,

Thanks for your post.

Please advise if the following code is correct:

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);

GPIOPinConfigure(GPIO_PQ4_DIVSCLK);

GPIODirModeSet(GPIO_PORTQ_BASE, GPIO_PIN_4, GPIO_DIR_MODE_HW);

SysCtlClockOutConfig(SYSCTL_CLKOUT_EN | SYSCTL_CLKOUT_SYSCLK, 100);

I also tried other 2 CLK source but still no waveform on the scope.

The register setting seems correct:

SYSCTL_DIVDCLK  0x80000063

PortQ-GPIO_AFSEL 0x00000010 (bit4)

PortQ-GPIO_PCTL 0x00070000 (bit4-DIVSCLK)

There is no ERRATA related to DIVSCLK.

The TI chip on the EK-TM4C1294XL is XM4C1294NCPDTI2.

The PQ4 configured as GPIO output seems works fine.

Do you have any clue?

Thanks in advance.

Ron

Hello Ron,

The original post from Tushar does cover the same. The missing line is in GPIO Configuration for enabling GPIODEN bit

GPIOPadConfigSet(GPIO_PORTQ_BASE, GPIO_PIN_4, GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD);

Regards

Amit

Hello Ron,

Following is the test code. I do see that when the System Clock is 120MHz, I get 1.2MHz on the PQ4 pad

    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);

    GPIOPinConfigure(GPIO_PQ4_DIVSCLK);

    GPIOPadConfigSet(GPIO_PORTQ_BASE, GPIO_PIN_4, GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD);

    GPIODirModeSet(GPIO_PORTQ_BASE, GPIO_PIN_4, GPIO_DIR_MODE_HW);

    SysCtlClockOutConfig(SYSCTL_CLKOUT_EN | SYSCTL_CLKOUT_SYSCLK, 100);

Regards

Amit

Hello Amit,

Thank you for the reply.

I already tried the code with GPIOPadConfigSet() API. It will lock the TivaC and drop the ICDI debug communication. No any connection to PQ4 yet.

Is it possible that my EK-TM4C129XL board has some special problem? It is Rev C with XM4C1294NCPD on it.

I got another EK-TM4C129XL board. it is the same.

I'm using CCS6.0.0.00190_win32 and tirtos_tivac_2_00_02_36. Is this same as yours?

Thanks.

Ron

Hello Ron,

I was working on this issue yesterday where someone else also had mentioned the same.

http://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/t/345762.aspx

Regards

Amit

Hi, Amit,

thank you very much.

I'll try to modify the board.

Ron

The code that will allow a clock signal out on DIVSCLK pin is shown below.

MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);
MAP_GPIOPinConfigure(GPIO_PQ4_DIVSCLK);
MAP_GPIOPinTypeGPIOOutput(GPIO_PORTQ_BASE, GPIO_PIN_4);

GPIODirModeSet(GPIO_PORTQ_BASE, GPIO_PIN_4, GPIO_DIR_MODE_HW);

SysCtlClockOutConfig(SYSCTL_CLKOUT_EN | SYSCTL_CLKOUT_SYSCLK, 4 );

Note that the first 3 lines of code comes from the PinMux c source file and are correct but you require the last two lines of code to get the output signal on the pin.

You must also cut trace from U4 pin 5 if you use a EK_TM4C1294XL eval board or you will get suddenly a message that the JTAG debugger could not connect.

The code example in spmu298a TivaWare Peripheral Driver Library will not even compile because the parameter names are completely wrong.

Example: Enable the PIOSC divided by 4 as the DIVSCLK output.
//
// Enable the PIOSC divided by 4 as the DIVSCLK output.
//
SysCtlClockOutConfig(SYSCTL_DIVSCLK_EN | SYSCTL_DIVSCLK_SRC_PIOSC, 4);

Manie

Is the output frequency limited by the clock driving the GPIO modules? I don't see any notable difference on my scope screen if I output 60 MHz SysClk with the "divide by 2" setting or 120Mhz with the "divide by 1" setting, both times I measure 60MHz with the Scope.

If it is in fact limited by the GPIO clock, one should make a note in the documentation that the "divide by 1" setting is useless for the sysclock.

Markus