Hi experts:
I have came across a problem when debugging the EMIF with external SRAM, the osc snea shows that the CS and Wen signal goes down and up for about 2 to 3 times in a write operation. This cause no problem in SRAM without FIFO, but for SRAM with FIFO, this causes troubles, since the unwanted up tp down transition can increase the pointer of the FIFO which causes incorrect results. Could help me to see this problem, it is a emergency, thank you very much!
Eric Fu.
Northwestern China MCU FAE
