CLK output on Tiva C Launchpad

Hello,

I am trying to generate the clk input for a TI ADS1278 ADC from the TIVA C series Launchpad with a Tiva C tm4c123gh6pm processor.  I would like a clock output that can run at a little less than 27MHz.  

The board, a custom launchpad booster pack, has a jumper to select between Port F1 (M1PWM5) and Port B4 (SSI2 CLK) with the intent to run the ADS1278 main clock either from the PWM output or the SSI CLK output.

First I have tried to use one of the PWM outputs, M1PWM5 on Port F1, to generate a 25 MHz output clk from a 50 MHz system clock.  I set the count of the PWM timer to 2, the pulse width to 1 and the PWM clk divider to 1.  This just outputs 3.3v.  However when I change the count to 4 and the pulse width to 2 I get the expected 12.5MHz output.  Is there some limitation that doesn't allow these counter settings?  If so, where is this stated in the documentation?  I have been looking for the minimum value for these settings, but haven't found any stated.

Second, I have considered running the clk input off the SSI2 CLK (Port B4) but I'm not sure how to setup the SSI port clk to continuously run.  Is there an easy way to do this?  How would I read from the device using SSI2 when in this configuration?

Third,  is there another method you would recommend to generate the required clock?  It needs to take up minimal CPU overhead.  Using a timer?  Some other method of outputting the clock or a divided version directly to a GPIO?

Here is the code I used for the setup of M1PWM5:

/**
 * Initializes the M1PWM5 to generate the clock for the ADC
 *  Utilizes PWM module 1 output 5 (PF1)
 *
 *
 *
 *  Clock Setup Options
 *  *25MHz    - 50 MHz system clock,    sysClkFreqDiv = ADC_PWM_DIV2
 *  *26.67MHz - 80 MHz system clock,    sysClkFreqDiv = ADC_PWM_DIV3
 *  *33.33MHz - 66.67 MHz system clock, sysClkFreqDiv = ADC_PWM_DIV2
 *	 (Need 2.0v < DVDD < 2.2v)
 *  /param sysClkFreqDiv - frequency divider of the PWM
 *  values: ADC_PWM_DIV2, ADC_PWM_DIV3
 **/
 void ADC_initClkM1PWM5(uint32_t sysClkFreqDiv) {
	// Setup GPIO config
	SysCtlPeripheralEnable(SYSCTL_PERIPH_PWM1);
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);

	GPIOPinTypePWM(GPIO_PORTF_BASE, GPIO_PIN_1);
	GPIOPinConfigure(GPIO_PF1_M1PWM5);
	SysCtlPWMClockSet(SYSCTL_PWMDIV_1);
	
	// Configure the PWM generator for count down mode with immediate updates
	// to the parameters.
	PWMGenConfigure(PWM1_BASE, PWM_GEN_2,
			        PWM_GEN_MODE_DOWN | PWM_GEN_MODE_NO_SYNC | PWM_GEN_MODE_DBG_STOP);
	
	// Set the period in number of clock cycles.
	//PWMGenPeriodSet(PWM1_BASE, PWM_GEN_2, sysClkFreqDiv);
	//PWMGenPeriodSet(PWM1_BASE, PWM_GEN_2, 2);
	PWMGenPeriodSet(PWM1_BASE, PWM_GEN_2, 4);

	// Set the pulse width.
	// PWMPulseWidthSet(PWM1_BASE, PWM_OUT_5, 1);
	PWMPulseWidthSet(PWM1_BASE, PWM_OUT_5, 2);

	// Start the timer.
	PWMGenEnable(PWM1_BASE, PWM_GEN_2);
	// Enable the output.
	PWMOutputState(PWM1_BASE,  PWM_OUT_5_BIT, true);
 }

Here is the output with a PWM count of 4 and a pulse width of 2:

Let me know if you need any other information.  I appreciate any help you can give.

Regards,

Curtis