Other Parts Discussed in Thread: HALCOGEN
I2C Driver in HALCoGen v03.08.01 (the same in v03.08.00) among other changes in compare with v03.06.00 has a different function i2cInit implementation.
The new one initialises MDR Register with following value:
i2cREG1->MDR = (uint32)((uint32)0U << 15U) /* nack mode */
| (uint32)((uint32)0U << 14U) /* free running */
| (uint32)(0U) /* start condition - master only */
| (uint32)((uint32)0U <<11U) /* stop condition */
| (uint32)((uint32)1U <<10U) /* Master/Slave mode */
| (uint32)((uint32)I2C_TRANSMITTER) /* Transmitter/receiver */
| (uint32)((uint32)I2C_7BIT_AMODE) /* xpanded address */
| (uint32)((uint32)0U << 7U) /* repeat mode */
| (uint32)((uint32)0U << 6U) /* digital loop back */
| (uint32)(I2C_RESET_OUT) /* Bring Out of Reset */
| (uint32)((uint32)0U << 4U) /* start byte - master only */
| (uint32)(0U) /* free data format */
| (uint32)(I2C_8_BIT); /* bit count */
and after that writes values to I2CCKL, I2CCKH and I2CPSC Registers:
/** - set prescale */
i2cREG1->PSC = 13U;
/** - set clock rate */
i2cREG1->CKH = 34U;
i2cREG1->CKL = 34U;
But there is a note it the description for I2CCKL, I2CCKH Registers in "RM46x 16/32-Bit RISC Flash Microcontroller. Technical Reference Manual" (SPNU514A–September 2013):
"This register must be configured while the I2C is still in reset (nIRS = 0)".
and for I2CPSC Register:
"This register must be initialized while the I2C is still in reset (nIRS = 0)".
The same code in the previous version of I2C Driver was written in accordance with this rules.
Actually, my old code doesn't work now (I use I2cInit), since I updated HALCoGen to v03.08.00 and then to v03.08.01. But now if I modify I2cInit so that I2C is kept in reset while other registers are being initialized and bring I2C out of reset at the end of this function, everything works properly.
Please, assure me that I do something wrong. :-)
