RM46L852 Hercules SPI problem

Judy,

I check the specification for your slave device, I the clock/phase configuration seems to be:
Clock Polarity 1, Clock Phase 0 as visible in the next picture:

Also, you are managing the CS as a GIO (Setting low and high manually)
Our SPI can do that automatically.

spitestcfg.CS_HOLD = 1;                                // CS will be held low during the full multi-data transfer.
spitestcfg.WDEL = 0;
spitestcfg.DFSEL = SPI_FMT_0;
spitestcfg.CSNR = SPI_CS_3;                        // CS_3 will be used.

Using the CS_Hold means that during the full transmission of your data, the corresponding CS (in this case CS_3) will be active low and will be release when all data have been transmitted.

 If you need to delay the transmission in relation to the falling edge of CS, this can also be done automatically.

NOTE: In Halcogen, the "Actual Delay" for C2TDELAY and T2CDELAY = 0 should be 0ns.
For all other value of C2TDELAY and T2CDELAY, the "Actual Delay" information is correct.

Please let me know if these information are helpful.

Hello Jean-Marc,

I'm managing CS as GIO. We want to control it by ourselves because of slave device. I changed CS_HOLD = 1; and Clock Polarity 1, Clock Phase 0. I made one mistake during first description, the data was 0x00, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xc2, 0x00, 0x00, 0x00, 0x01, 0xae. After I made change, the data became 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc2, 0x00, 0x00, 0x00, 0x01, 0xae. If I changed SPI_CS_3 to SPI_CS_NONE, it didn't change result. Is there any special requirement if I configure CS as GIO?Thanks!

Judy

Judy,

Now I'm confused.

It is fine to manage CS by yourself if this is what you need.
In this case I will configure all CS as GIO (in Halcogen SPI3 port tab)
For the one used to select your slave device, be sure to have the default state as output 1. (It is the case in the Halcogen project you posted)

The CS_HOLD = 1 is only valid when SPI manages the CS automatically.

Can you confirm that with Clock Polarity 1 and Phase 0 you are getting the correct data.

Hello Jean-Marc,

I have tried the following ways, but no luck.

1. CS_HOLD = 1,  Clock Polarity 1 and Phase 0, CS3 was configured as SPI function, the data received 0x00, 0xff, 0xff, 0xff, 0xff,0xff,0xc2, 0x00, 0x00, 0x00, 0x01, 0xae, I expected is 0xe1, 0x00,0x00,0x00,0x00,0x00,0xd7

2. CS_HOLD = 0, Clock Polarity 1 and Phase 0, CS3 was configured as GIO function, default output is 1, CSNR= SPI_CS_NONE, the data is same as above.

3. CS_HOLD = 0, Clock Polarity 1 and Phase 0, all CS were configured as GIO function, default output is 1, CSNR= SPI_CS_NONE, the data is same as above.

Thanks,

Judy

Judy,

I looked at your code, and I'm not sure I understand what you are doing.

First you are doing:

1] Activate CS Low.
2] spiSendData(spiREG3, &spitestcfg, 11, data_WCFGR0); 
    This will send 11 bytes from data_WCFGR0 to your slave device. You don't care about the 11 incoming bytes.
3] Activate CS High.
4] Activate CS Low.
5] spiSendAndGetData(spiREG3, &spitestcfg, 16, data_RCFGR0, data_recv);
    This will send 16 bytes from data_RCFGR0 to your slave device and will store the 16 incoming bytes to data_recv. What I don't understand is the way data_RCFGR0 is defined.

uint16 data_RCFGR0[16] = {0x80, 0x49, 0x02, 0xce, 0x00, 0x00,0x00,0x00,0x00,0x00,0x00};
Only 11 data are defined here. Hopefully the next five will be 0x00.

6] Activate CS High.

Is it really what you want to do?

Jean-Marc,

Yes, this is what I want to do. 

The first 4 byte data_RCFGR0 is read command. The following 0x00 is for data shift out.

Thanks,

Judy

Judy,

After reading the LTC6803 specification I start to have a better understanding.
There is still one point I don't catch.
In your Write command you have:

uint16 data_WCFGR0[11] = {0x80, 0x49, 0x01, 0xc7, 0xe1, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd7};

spiSendData(spiREG3, &spitestcfg, 11, data_WCFGR0);

Chip Select Low.
0x80 is your Board Address.
0x49 is PEC for Board Address.
0x01 is the Write Configuration Register Group command.
0xc7 is PEC for WRCFG.
0xe1,is write Data for CFGR0.
0x00,is write Data for CFGR1.
0x00,is write Data for CFGR2.
0x00,is write Data for CFGR3.
0x00,is write Data for CFGR4.
0x00,is write Data for CFGR5.
0xD7 is PEC for the 6 last Data.
Chip Select High.

What is the board address? I don't see that in the specification.

uint16 data_RCFGR0[16] = {0x80, 0x49, 0x02, 0xce, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};

spiSendAndGetData(spiREG3, &spitestcfg, 11, data_RCFGR0, data_recv);

Chip Select Low.
0x80 is your Board Address.
0x49 is PEC for Board Address.
0x02 is the Read Configuration Register Group command.
0xce is PEC for RDCFG.
0x00 is dummy data to receive CFGR0.
0x00 is dummy data to receive CFGR1.
0x00 is dummy data to receive CFGR2.
0x00 is dummy data to receive CFGR3.
0x00 is dummy data to receive CFGR4.
0x00 is dummy data to receive CFGR5.
0x00 is dummy data to receive PEC for last 6 Data.
Chip Select High.

Because the spiSendAndGetData is used to read the data from LTC6803, all 11 data will be available in data_recv. 
data_recv[0] = dummy.
data_recv[1] = dummy.
data_recv[2] = dummy.
data_recv[3] = dummy.
data_recv[4] = CFGR0.
data_recv[5] = CFGR1.
data_recv[6] = CFGR2.
data_recv[7] = CFGR3.
data_recv[8] = CFGR4.
data_recv[9] = CFGR5.
data_recv[10] = PEC.

Please correct me if I've missed something.

Hi Jean-Marc,

Correct, the board address is 0x00

Judy,

Ok, now I see. I was using the specification for LTC6803-1/LTC6803-3.
You are using LTC6803-2/LTC6803-4

Sorry to ask you that question, but you are using the correct part? (-2 or -4)
If yes, I assume A0, A1, A2 and A3 pins are connected to gnd (Pins 37, 38, 39, 40)

Hi Jean-Marc,

Yes, I'm using LTC6803-2. I sent question to LTC too. I will let you know if they have any update.

Thanks,

Judy