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TM4C123GH6PM PWMn Control (PWMnCTL) question

Other Parts Discussed in Thread: TM4C123GH6PM

Can please someone explain the following inconsistency in the TM4C123GH6PM datasheet.

For register PWMn Control bits LATCH and MINFLTPER there is a note:

"When using an ADC digital comparator as a fault source, the LATCH and MINFLTPER bits in the PWMnCTL register should be set to 1 to ensure trigger assertions are captured."

At the same time for MINFLTPER bit:

"The delay function makes sense only if the fault source is unlatched. A latched fault source makes the fault condition appear asserted until cleared by software and negates the utility of the extend feature."