what should i do to generate a code for PBIST with the HALCoGen

John,

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Hello John,

  In the HalcoGen under the SAFETY INIT tab, you can select which memory that you want to perform PBIST test on. Once you generate the code you will see two functions related to PBIST testing. One is pbistSelfCheck() and another is pbistRun(). pbistSelfCheck is used to run a diagnostic on the PBIST controller itself making sure that it can detect and report a test failure. pbistRun() is what you call to initiate memory test on the on-chip memories. See these function calls and definition in sys_startup.c and sys_selftest.c.

Hi Charles,

I'm using the device "TMS570LS20216ZWT".

I have no the tab "SAFETY INIT" in the HALCoGen, but the tab "PBIST".

In this tab, i can enable triple read fast/slow test.

After that, i got a function _memoryTest_( ). It's declared in "sys_memory.c", and defined in "sys_memory.asm". It also declared two notification :memoryPort0TestFailNotification(), memoryPort1TestFailNotification().

It will be called in "sys_startup.c", between systemInit() and _memoryInit().

I wanna know it is right for a PBIST test?

Hello Charles,

   Thank you for your help.

   Now, i figured out my question.

   I wanna know if i can use the PBIST code of TMS570LS31 generated by HALCoGen in the TMS570LS20216 project directly?

  The TMS570LS20216 PBIST Module is the same with TMS570LS31?

Hello John,

  I would not recommend using PBIST code generated from HalcoGen for TMS570LS31 to be used on TMS570LS20216. The reason is that the code generated for TMS570LS31 is specific to TMS570LS31 for its RAM groups and supported algorithm. The TMSLS20216 has slightly different RAM group organization and also some difference in terms of the memory type. For example, in LS31x, the VIM RAM is at group 10 while in 20216 the VIM RAM is at group 8. If you look at the memory type, in LS31x the DCAN RAM is of dual-port while the 20216 is of single port RAM. Therefore, different algorithms need to be applied to different type of memory. You will need to look at the differences between the two devices for their PBIST Memory Grouping very carefully to know what algorithms to apply to what memories. To save yourself the hassle I will not recommend doing so.

regards,

Charles

Hello Charles,

You mentioned in the last mail :
" If you look at the memory type, in LS31x the DCAN RAM is of dual-port while the 20216 is of single port RAM."

I thought  DCAN / MibSPI / MibADC / HET RAM are always Dual Port because it has to have either simultaneous READ from CPU and WRITE from Peripheral Side or vice versa.
Is that not TRUE for LS20216 device?
Some technical description will help me understand better about the meaning of DUAL PORT and SINGLE PORT.

Thank you.
Regards
Pashan

Hello Pashan,

  LS20216 is based on an older technology node. Some of the memories such DCAN RAM is based on single port memory. This is different compared to LS31x/LS12x/LS04x which is based on newer technology. Single port memory is a clocked synchronous memory. An address is given to the Single Port memory with some setup time before the clock. The data is returned with some access time synchronous to the clock edge. Dual-Port or I would rather call it a Two-Port RAM to be more precise is a asynchronous memory. There is no clock involved. An address is given to the Two Port RAM, and after some access time the data will be valid from the time the address is valid. Two Port memory does not necessarily mean that the memory controller (i.e. DCAN RAM controller) will utilize the capability to read by one master and write by another master simultaneously even though the capability is there. It all depends on which memory controller you are talking about. One example is NHET. It is in fact allowing CPU or DMA to read/write to the NHET RAM while the NHET state machine is also reading and writing to the RAM at the same time.

regards,

Charles