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TMS570 PBIST

Other Parts Discussed in Thread: HALCOGEN

I am trying to understand, in case of the PBIST failure, how to identify which RAM group failed by looking at FSRDL0 and FSRDL1. It is not specified in the TRM or the datasheet. I assume that it is the same mapping as the RINFO. Would that be correct aasamption?

Thanks,

Alex 

  • Alex,

    We have received your question and it has been forwarded to our PBIST expert. They will contact you as soon as possible.

  • Hello Alex,

      If there is a PBIST fail, you will first look at the RAM Configuration Register (RAMT) in the PBIST module to find out which RGS and RDS the memory fails the PBIST.  You will then refer to another table titled "PBIST Memory Grouping" in the TRM to find out which memory the RGS:RDS corresponds to. I'm using (spnu499b) the TRM for  LS31x/21x family for reference below. Below only shows portion of the table.

    regards,

    Charles

     

  • Charles,

    So according to this you can only see one failure at the time, but when you execute an algorithm it will be executed on more than one group of RAM. Does it stop execution on first failure. If so, in what order is the test excuted? Is the RDS number mean anything when a range of numbers is defines for the RAM group?

    Thanks,

    Alex

  • Hello Alex,

       Let's use DCAN1 which is mapped to RAM group 5 as an example. You see the corresponding RGS=3 and RDS=0..5. The reason that the RDS (RAM Datapath Select) is in a range is because physically a RAM bank instance can have a wide memory width. In the case of the DCAN memory. It consists of two physical memory bank instances. One bank has a memory wdith of 103bit and the other has a width of 42bits. These 103+42=145bits of data path is divided into 6 different RDS. The PBIST engine will try to evaluate/compare each RDS of datapath at a time. At any one time one RAM group is tested. Note that one RAM group may consist of multiple memory banks. The PBIST engine stops executing the memory self-test whenever a failure occurs in any memory instance for any of the test algorithms.

    regards,

    Charles

     

     

  • A minor correction. The DCAN1 is mapped to RAM group #3, not #5. #5 is for DCAN3.

  • Hi Charles,

    If the test stops on any failue, what is the order of execution in case I select the test algorithm on all devices that support this algorithm (like the HALCOGEN does)? Is it in the order of the RAM group number? If that is the case, I need to select the algorithm to test only one group at the time, per the order of importance for me.

    Thanks,

    Alex

  • Hello Alex,

      It should go according to the order of the RAM group number. I will double check on this and get back to you.

    regards,

    Charles

  • Hello Alex,

      I just checked that the PBIST testing will run in the order of the RAM group number.

    regards,

    Charles