PLL1 and PLL2

Brice,

GCLK, HCLK, VCLK1, VCLK2, VCLK3 are all based on the same clock source.
This clock source could be any of the 7 clock (Oscin, PLL1, PLL2, LPO_Low, LPO_High, Ext1, Ext2)

N2HET (VCLK2) and ADC (VCLK1)  are using the same source, but can have different prescaler.

So your option is not possible,

Hello Brice,

  There is a requirement that the VCLK2 must be an integer multiple of VCLK frequency. Setting both VCLK and VCLK2 to 110MHz is ok. Wouldn't that work for you?

regards,

Charles

Hi Charles, Jean-Marc,

Actually I need to generate a clock which frequency is given by an external parameter, So it could be precisely 4 MHz or 1 MHz for instance. 

With VCLK2 = 110, it is easy to adjust the hr and lr value (for instance hr=55, lr=1 ) to get generate a clock of 1 MHz

with the same VCLK2, 4 MHz is unachievable.

To achieve 4MHz with a decent number of instructions in the HET program I can use VCLK2 = 80 hr=10 lr=1 (so 10 instructions max)

In the same time I don't want to deteriorate the ADC sampling frequency based on VCLK1 and driven by the same

clock source !

thank for your answer.

Brice

Do you have a clu on a way to generate a 4 MHz clock with VCLK  = 110 ?

Brice,

  Does it need to be precisely 4MHz? Can you live with some tolerance? For example, will either 3.93MHz or 4.07MHz work for your application? 4.07Mhz will be about 1.75% off from 4MHz. Also must you have a 50% duty cycle high phase and low phase on the clock?

  I was thinking setting lr=16 and hr=1 and utilize the high resolution delay. For example, creating a 4.07MHz clock with 11 High resolution clocks of high phase and 16 high resolution clocks or low phase. One high resolution clock will be 9.09ns. The period of the clock will be 9.09 * (11+16) = 245.43ns which is about 4.07MHz.

regards,

Charles

hi Charles,

actually a signal of data is synchronized to this 4MHz clock and read on the rising edge. I tried with some clock slighty different of 4MHz but there is a de-phase after a while.

I will try your method (next week) to see if this decalage is not significant.

I will let you know

thank you for your help 

Hi Brice,

  OK, if the data is synchronized to the edge then the duty cycle is probably not the big problem if it is not 50%. Let me know if your result using high resolution delay method.

regards,

Charles

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Hi Charles,

I thought about your idea, and I don't really figure out how you can manage to create this 4.07 MHz signal since by using  11 hr period for the high phase and 16 hrp for low phase you come to a point where you need to modify the output pin twice in the same cycle, which is obviously not possible.

for instance : let say the high phase starts on the 1st hrp of the cycle 0

C0_hrp1:high phase ....C1_hrp11:low phase....C2_hrp11:high phase....C3_hrp6:low phase.....C4_hrp1:high phase

--> problem at Cycle 4 the delay = 1   :

the low phase need to start at hrp = 12 to keep 11 high resolution period for the high phase

so I still don't figure out how you can generate this signal.

thank for your help 

Brice

Hi Brice,

  I was thinking using just CNT and ECMP instructions. In the CNT you will set the max count = 2. In the ECMP instruction the compare value will be 1 with a high resolution delay of (16-11)=5. The pin action will be PULSEHI. However, in every alternate loop resolution the max count and the compare value will need to change to 1 and 0. Let me think about it more to see if it will work.

regards,

Charles

Do you think it might be possible using XOR on two consecutive pins ?

there may be an idea there ? what do you think ?

Hi Brice,

  I'm not able to get it to work with my original idea. Need to experiment a bit more.  I'm not too sure if XOR of two pins will generate what you needed which is 4MHz output with the VCLK2=110MHz.

regards,

Charles