I have isolate the function of the selftest ccmselftest()
After CCMKEYR =0x6U the register is set in the CCS register, but the selftest never complete. Whats wrong ?
(CCMSR is never set to 100U)
The PCR PPROTSETx and PMPROTSETx registers are not decribed in the manual (SPNU514A
September 2013)
Isolating function checkFlashECC will not initiate a change of the FEDACSTATUS ? Whats wrong ?
Best regards A. Friebel
Hello Arne,
About CCM: As I mentioned earlier the CCM selftest can only be run when you don't have the debugger connected. The Data Manual also briefly mentioned in the CCM section. HalCoGen provides the ccmSelfCheck() function. In the SAFETY INIT tab in HalcoGen you can select the checkbox for Enable CCM Self Test. HalcoGen will generate code to call the ccmSelfCheck() in the sys_startup.c. Please give a try after power up reset. To demostrate this maybe put a simple while (1) statement in your main(). Once you connect to the target, you should see that the code is in the while(1) loop. This means the ccmselfCheck() has been run.
About PCR: Sorry that it creates some confusion to you. Please take a look at the below snippet table that shows what peripherals are mapped to what peripheral selects. I'm using literature number spns185a for the device RM46L852 for reference. You will need to reference the datasheet that is specific to your device. In the same table you will also find the peripheral memory select information. Some peripherals may share the same peripheral select. A peripheral select can be subdivided into 4 quadrants. For example, you wil find that HTU1 and HTU2 both share the same peripheral select 22 but of different quadrants.
About PMU: The PMU is part of the CPU. You wil find details about PMU in the Cortex-R4 TRM. Please find below snippet about PMU control register and the X bit. Enabling the X bit will allow the ECC errors detected by the CPU to notify the flash module to update its EDACSTATUS register.
About PLL2SLIP and checkClockMonitor: I don't see them stuck in the loop. I created a simple test and invoke these two selftest functions in the main() and don't see any problem. You can try it. Whether I single step or just free run, I will always finish in the while (1) loop.
void main(void)
{
/* USER CODE BEGIN (3) */
checkPLL2Slip();
checkClockMonitor();
while (1);
/* USER CODE END */
}
The project is attached below.
7563.LS31_Flash_Diagnostic_Mode_7.zip
Hello Arne,
My asnwers are embedded below.
About CCM: I have tested it and without connected debugger it works. I can see it on the behaviour of some ports. You mention that you connect the debugger after it has passed the test. How do you do this. Do you disconnect the JTAG Port or the USB cable to the debugger. In which state should be the CC5-SW. When you start debugging in CC5 you have to press the debug buttom and a reset will happen and a new download of the programm will start. So that could not be the state, or. If you press run, the test will hang-up, because of the debugger and so its also not the state. So how do you do this ? In stop mode ?
CT>> This is what I do.
1. Load the program. This will flash the device
2. In the CCS Debug Perspective, under Run tab, select the Disconnect Target
3. On your board, press the reset
4. In the CCS Run Tab, select the Connect Target again
If you have a while(1) in your main() then you should see the code already in the while loop. You might need to load symbol also but I didn't need to do this.
About PCR: Is it like this, the PS22 Bit will include the two memory sectors of HTU1 and HTU2. (This memory contains registers and RAM area) When I set this bit the registers inside these memory, that means the HTU1 and HTU2 registers can only be written in privileged mode. If this bit is not set, you can read or write all registers for HTU1 and HTU2. Is it like this ?
CT>> The PS22 is for the HTU's registers. HTU has a separate RAM where it stores the control packets. The HTU RAM has separate peripheral memory select. Please see below. You should find them in the Device Memory Map table in the device datasheet. As you can see the HTU1 RAM is mapped to PCS[39] and HTU2 RAM is mapped to PCS[38].
And whats the privileged mode writing. What must I do there ?
CT >> By default you should be in privilege mode after reset.
About PMU: As you said, the X-bit is not set correctly for this test (all others work, like checkRAMecc, checkFlashEepromEcc and so on). So after leaving the start-up routine the bit must be changed, or. Is this bit only relevant for that test ? Or if I change the bit setting all others failed ?
But first, as I understand for the test the export must be enabled (set to 1) and for normal operation the bit must be set to 0. Is it like this ?
CT>> If you use HalCoGen to generate the startup file, the X bit will be set as part of the function call to _coreEnableEventBusExport_() in the sys_startup.c file. The Cortex-R5 CPU outputs various different events to the system. ECC errors detected related to flash on the ATCM side and as well as RAM on the BTCM side will be signalled to the flash and RAM modules. Enabling the X bit will not make other tests fail.
In the sys_core.asm exists a command
_coreEnableFlashEcc_
Can I do this with that command ? Here the comments are very bad. It would be helpfull, here to have a little sentence like "Setting .... for....doing....". A little explaination what the function does, will be very helpfull.
CT>> Thanks for the feedback. This function call is to enable ECC checking for the ATCM interface memory. It will set the bit 25 ATCMPCEN of the Auxiliary Control Register inside the CPU.
About NOP: I am seaching for the nop command
CT>> You can do inline assembly as below if you are looking to insert a NOP.
asm(" NOP");
About CC5: Inside the Flash Wrapper Register View the Registers from FRDCNTRL up to FEDACSDIS2 are visible, the rest 288hex starting with FSM_WR_ENA up to FCFG_BANK (in the manual page 276) are not there. Why ?
CT>> Many of the registers are related to flash programming and EEprom bank configuration and diagnostic. Currently it is showing the registers that are mostly used by the users. The XML for the flash module could be updated in the CCS to show these register. Need to check on the CCS release plan. In the meantime if you really need to view these registers please use the memory browser and specify these register addresses. You can view them there.
About CheckClockMonitor: I have a hang-up, but I have to check your files and the setting, it will take a while.
CT>> Let me know your result.
About PBIST and STC: Can the tests be made with the debugger, or not like CCM ?
CT>> Yes, you can run them with the debugger connected.
regards,
Charles
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