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TMS570 does not release I2C bus?

Tom Major
Intellectual 260 points


Hello,

I am reading/writing periodically to the I2C bus and have sometimes a problem with the master bit.

According to the manual "Before starting the next transaction in master mode, this bit must be confirmed to
be cleared."

Sometimes this bit is not cleared and my atempt to clear it will fail. I have then to reinit the I2C (reset bit).

The code for trying to clear the master bit at the beginning of the routine is like this:

  to = I2C_TIMEOUT; //10
  while (i2cREG1->MDR & I2C_MASTER) {
    i2cREG1->MDR = I2C_MASTER | I2C_RESET_OUT | I2C_TRANSMITTER | I2C_STOP_COND;
    delay_us(5);
    to--;
    if (!to) {busy = true; break; }
  }
Do I miss something here? Why is the master bit not cleared from the previous transfer and even if so, how can I cleanly clear master mode to start anew (without doing a I2C reset)?

Thank you very much,

Tom

  • 0
    TI__Guru 59540 points

    Hello Tom,

    The TRM states that the MST bit is reset after a STOP condition. However, the STOP condition being set by hardware is conditional based on what mode you are using (non-repeat mode, RM=0 or repeat mode RM=1). Please check which of these modes you are using and let me know. If you are in repeat mode, try manually forcing a stop condition after your transmission is completed to see if this clears the BB and then MST bits.

  • 0 in reply to Chuck Davenport
    Intellectual 260 points

    Hello Chuck,


    thanks for the quick reply. I am in non-repeat mode and in non-free data format mode.

    I try to manually force a stop condition with the code I posted above, this line:

    while (i2cREG1->MDR & I2C_MASTER) {
        i2cREG1->MDR = I2C_MASTER | I2C_RESET_OUT | I2C_TRANSMITTER | I2C_STOP_COND;

    why does this not work?


    Thanks,

    Tom

  • 0 in reply to Chuck Davenport
    TI__Guru 59540 points

    Hi Tom,

    In your original post, you mentioned that "sometimes" the MST bit is not cleared and you are forced to reset the module. Are you able to capture the wave forms of the I2C transmission in both cases and, if so, do you see any differences? i.e., are there stop conditions shown in both cases or only in the cases where MST is cleared by the hardware?

    Additionaly, when MST is not cleared after a transmit, can you check the value of the ICCNT register to insure it has rolled past 0 which is a condition that must be met to send the stop condition on the bus.

  • 0 in reply to Chuck Davenport
    Intellectual 260 points

    Hello Chuck,


    no, I have not yet captured the waveforms for this, but will try in the next days. I will get back with some more data, hopefully.

    Thanks,

    Tom

  • 0 in reply to Chuck Davenport
    Intellectual 260 points

    Hello Chuck,

    I did some wave form measurement and could not discover any differences.

    I think I found the problem, though. In my code, I had a place which set the stop bit when a timeout / error occurred.

    i2cREG1->MDR |= I2C_STOP_COND | ...

    But this place was hit also in normal condition once the read/write loop was done. So I guess under certain circumstances this second set of stop bit (first set automatically by CNT zero logic) was the reason for sometimes not getting a free bus. Without this it runs stable now, bus is always free after transmission so far.

    Thanks,

    Tom