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TMS570 Flash error reporting vs. ESM channels

Henry Abril1
Intellectual 485 points

Other Parts Discussed in Thread: TMS570LS3137

Hi,

I have found the following information in the document:

TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller

SPNS162B –APRIL 2012–REVISED JULY 2013

4.19 Reset / Abort / Error Sources

----------------------------------------------------------------------------------------------------------------------------------------

FLASH

...

1.35 - FMC correctable error - Accesses to EEPROM bank

1.36 - FMC uncorrectable error - Accesses to EEPROM bank

1.6  - FMC correctable error - Bus1 and Bus2 interfaces (does not include accesses to EEPROM bank)

 

2.4  - FMC uncorrectable error - address parity error on Bus1 accesses

3.7  - FMC uncorrectable error - Bus1 accesses (does not include address parity error)

3.7  - FMC uncorrectable error - Bus2 accesses (does not include address parity error and EEPROM bank accesses)

----------------------------------------------------------------------------------------------------------------------------------------

 

Could you please help me to clarify the following items:

1.)  As far as I know the CPU is accessing the EEPROM, ECC and OTP memory areas via the bus2 interface and the bus1 is connected to the TCM Flash. Right?

2.) Are ALL the EEPROM errors reported only through the ESM channels 1.35 and 1.36?

2a.) Does the channel 1.36 covers EEPROM address parity errors?

3.) Are the address parity errors on Bus2 (OTP, ECC) accesses reported? Which ESM channel covers that error reporting? Where can I find that information in the TRM or in the TMS datasheet?

Thank you,

Henry

 

  • 0
    TI__Guru**** 191886 points

    Hello Henry,

      Please find my answers.

    1.)  As far as I know the CPU is accessing the EEPROM, ECC and OTP memory areas via the bus2 interface and the bus1 is connected to the TCM Flash. Right?

    CT>> Your understanding is correct.

    2.) Are ALL the EEPROM errors reported only through the ESM channels 1.35 and 1.36?

    CT>> That is correct. All EEprom related ECC errors are mapped to 1.35 and 1.36.

    2a.) Does the channel 1.36 covers EEPROM address parity errors?

    CT>> No. Bus2 does not perform address parity check. Only Bus1 does. Address/Control parity generation is built into the Cortex-R4 CPU's TCM interface. Bus2 is connected to the CPU's AXI interface. The AXI interface on the R4 core does not support address/control parity.

    3.) Are the address parity errors on Bus2 (OTP, ECC) accesses reported? Which ESM channel covers that error reporting? Where can I find that information in the TRM or in the TMS datasheet?

    CT>> As answered in 2a, there is no address parity error detection for Bus2. However, the ECC encoded for the data stored in the EEprom bank and OTP sectors is based on both the address and the data. Also the two CPUs are in lockstep and constantly being compared on its outputs. This includes also the AXI interface. So if there is an address generation fault from one CPU, the CCM will have the diagnostic to catch the miscompare.

    regards,

    Charles