Hello,
I am having a problem with SPI in compatibility mode. The CS_HOLD bit isn't working properly in my configuration.
In order to keep the CS pin low during an N bits transmittion you need to write 1 to the CS_HOLD bit in SPIDAT1. And in the final transfer it must be set to 0 (zero) for it to rise again.
I am doing this but I can't see the CS pin going to 3v3 in my oscilloscope.
Here's my code:
for (i = 0; i < SIZE; i++) {
send((uint8_t *)addr++, i);
}
Which in turn calls this:
uint32_t send(uint8_t *data, uint32_t bytesLeft) {
uint32_t csHold = SPI1_config.hold;
if (bytesLeft == 1) {
csHold = 0;
}
SPI1_send_byte(data, csHold);
return 1;
}
Which in turn calls this:
static void SPI1_send_byte(uint8_t *data, uint32_t csHold) {
uint8_t spiBuf;
uint32_t reg;
while (!(SPI1Reg->SPIFLG & 0x200U));
reg = *data | (SPI1_config.CS << 16) | (csHold << 28);
SPI1Reg->SPIDAT1 = reg;
spiBuf = SPI1Reg->SPIBUF;
}
And they use this structure:
static struct spi_config_data SPI1_config = {
.baud_MHz = 1,
.n_Bits = 8,
.CS = 0xFE,
.mode = 1,
.hold = 1
};
As I saw in the code generated by HALcogen, it is doing exactly this. It sets the CS_HOLD bit in SPIDAT1 from the first transmission to the N-1. Clearing it to 0 in the last transaction.
