PLL usage when byapss bist sets.

Hello Kyt,

The PLL is not usable when the Bypass bit is set. The Bypass bit decides if the system clock which is sent to almost all modules is derived from PLL%SYSDIV or OSC%SYSDIV

Regards

Amit

In followed case, does Tiva operate correctly?

  ADC CLK=Main OSC( with PLL)

  System clock = Main OSC(bypass)

Is ADC clk  set up MainOSC(bypass) compulsorily  in case of your indication?

bestr egards,

kyt

Hello Kyt,

Yes. If the ADC Is set up for the value 0x0 then it will derive the clock based on the PLL bypass or not. If PLL is bypassed then it will use MOSC clock, if not then it will divide the clock to get 16MHz.

Regards

Amit

Hello Amit,

5.3 Initialization and Configuration describes procedure of PLL configuration.

If skip procedure 5." Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2." , can PLL output and other oscillator(selected by OSCSRC register) operate independently?

best regards,

kyt

Hello Kyt

If the PLL is bypassed, then please use only MOSC or PIOSC as the clocking option. Using LFIOSC would be a very low speed clock which may cause JTAG to be disconnected.

Also if PLL has to be used later then the OSCSRC of MOSC and PIOSC can be used for locking the PLL

Regards

Amit

Hi Amit,

I appreciate a very quick reply deeply.

If it does so, is it right at an understanding that it cannot operate independently?

Or is it better to try on the EVM?

best regards,

kyt

Hello Kyt

If the question is whether PLL and OSC can act independently as System Clock, then it is a yes. At any given time either PLL or OSC will be the system clock source. I hope that clarifies the doubt you have? If no, then I would ask you to put the confusion you may be having regarding the Clocks as points 1-2-3.

Regards

Amit

Hi Amit,

I appreciate a very quick reply deeply　again.

For the synchronization with the surrounding device, I would like to shorten T_delay as much as possible.

However, since the time is prescribed by hardware, it is difficult to do short.

Then, it is being examined whether clock source changes, after the PLL lock.

First, TivaC operates default clock(PIOSC).

Sencondly, PLL enable,but system clock is stay in PIOSC.

Next, check the lock bit, PLLSTAT register.

Finally if PLL lock, change PLL output from PIOSC.

Is it the right understanding although I think that it can do in old questions and answers?

Is API which carries out such operation prepared?

best regards,

kyt

Hello Kyt

The API is SysCtlClockSet

There are example code which will tell how to lock the PLL from MOSC for 80MHz.

SysCtlClockSet(SYSCTL_SYSDIV_2_5 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ |
                       SYSCTL_OSC_MAIN);

Regards

Amit

Hello Amit,

It was understood that it was necessary to make it by oneself since API is not prepared.

betregards,

kyt

Hello Kyt,

The API is well prepared and has been extensively used. If you can please list out why you want to write the API again yourself, it would perhaps make my assumptions clearer.

Developing the API by yourself is good, but if it already exists then mistakes would be tougher to correct and long term code maintenance would be a problem too.

Regards

Amit