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Flash Module Controller: Confirmation regarding bit fields in FEDACSTATUS

oliver.gruendonner
Intellectual 830 points
Other Parts Discussed in Thread: TMS570LS3137

Hi.

My question is regarding the TMS570LS3137.

In spnu499b.pdf, page 269 to 271, are the bit fields of register FEDACSTATUS described. Can you confirm that the Description of the following two bit fields are correct:

* ERR_ONE_FLG

* ERR_ZERO_ FLG

Two reasons for this question:

* Reason 1: In ERR_ONE_FLG is ONLY "bus 2" stated, but not "bus 1". But in ERR_ZERO_ FLG is "bus 1" and "bus 2" sated. Why this difference?

* Reason 2: In ERR_ZERO_ FLG is stated "This bit is set if ..., or if either the EZFEN or the EOFEN bits are set and any single bit error is detected and corrected on bus 1. ...". Why  should an enabled EOFEN (Error on One Fail Enable) bit and a single bit error lead to setting of ERR_ZERO_ FLG (Error on Zero Fail Status Flag)?

Thank you and regards

Oliver.

  • 0
    TI__Guru**** 184056 points

    Hello Oliver,

      Flash module has both Bus1 and Bus2 interface. Bus1 is connected to the CPU's ATCM interface. ECC error detection and correction is carried out by the CPU for errors happening on the Bus1. When there is a correctable ECC error detected by the CPU it will be corrected but however the CPU's SECDED logic does not distinguish a correctable error is a result of a flipping bit from one to zero or from zero to one. It will only signal to the outside world via the event bus that a correctable error has been detected. The flash module will use this event bus signal to set the ERR_ZERO_FLAG regardless if a correctable error is due to one to zero flip or a zero to one flip. 

      Bus2 is connected to the CPU's AXI interface. There is no ECC error detection circuity built inside the CPU for the  AXI interface. Access to the EEprom and OTP is done through the flash module's Bus2 interface. The flash module contains a local SECDED logic just for the Bus2 interface. Since this is a built in error detection logic it has the extra smartness to know if a correctable ECC error is due to a one to zero flip or a zero to one flip. So it can set the appropriate bit accordingly.

    regards,

    Charles