SSI0 IntRegister Question

Hi,

I am using TM4C123BH6ZRB/LM4F212H5BB with IAR Embbeded Workbench. I have no problem in using the static interrupt vector table to register the callback functions for UART0, SysTick, ADC sequence 0, etc. These peripherals function as expected.

I also registered the same way for "Slave" SSI0 Rx interrupt handler in the interrupt vector table. However, I do not get the SS0 Rx interrupt unless I add the dynamic interrupt registration with IntRegister();

I would like to remove the call to IntRegister() in the SSI driver since the static configuration in the interrupt vector table should work but it doesn't. Please let me know what could be the reason.  Thanks.

__root const uVectorEntry __vector_table[] @ ".intvec" =

{
{ .ulPtr = __section_end( "CSTACK" ) }, // The initial stack pointer
{ .pfnHandler = ResetVector }, // The reset handler
{ .pfnHandler = NmiSR }, // The NMI handler
{ .pfnHandler = FaultISR_Decoder }, // The hard fault handler
{ .pfnHandler = FaultISR_Decoder }, // The MPU fault handler
{ .pfnHandler = FaultISR_Decoder }, // The bus fault handler
{ .pfnHandler = FaultISR_Decoder }, // The usage fault handler
{ .pfnHandler = 0 }, // Reserved
{ .pfnHandler = 0 }, // Reserved
{ .pfnHandler = 0 }, // Reserved
{ .pfnHandler = 0 }, // Reserved
{ .pfnHandler = IntDefaultHandler }, // SVCall handler
{ .pfnHandler = IntDefaultHandler }, // Debug monitor handler
{ .pfnHandler = 0 }, // Reserved
{ .pfnHandler = IntDefaultHandler }, // The PendSV handler
{ .pfnHandler = EC_Tick }, // The SysTick handler
{ .pfnHandler = IntDefaultHandler }, // GPIO Port A
{ .pfnHandler = IntDefaultHandler }, // GPIO Port B
{ .pfnHandler = IntDefaultHandler }, // GPIO Port C
{ .pfnHandler = IntDefaultHandler }, // GPIO Port D
{ .pfnHandler = IntDefaultHandler }, // GPIO Port E
{ .pfnHandler = USART_IRQHandler }, // UART0 Rx and Tx
{ .pfnHandler = IntDefaultHandler }, // UART1 Rx and Tx
{ .pfnHandler = SFTY_IntHandler }, // SSI0 Rx and Tx

. . . . . 

// SSI0
SPI_Enable( SAF_SPI_BASE );// Enable RX timeout interrupt (asserted 32 bit clocks after a word is

// written to the empty RX FIFO) and half-full.
SPI_IntEnable( SAF_SPI_BASE, SSI_RXFF | SSI_RXTO );

// Read any residual frames
status = SPI_ClearRxFifos();

// Clear any pending interrupt
SPI_IntClear( SAF_SPI_BASE, SSI_RXFF | SSI_RXTO );

// Remove this registration will cause Rx interrupt won't work
SPI_IntRegister( SAF_SPI_BASE, SFTY_IntHandler );