TCRAM: Read-clear needed also for RAMSERRADDR?

oliver.gruendonner

Hi.

My question is regarding the TMS570LS3137.

In spnu499b.pdf is stated the following:

* For register RAMUERRADDR, page 314, Table 6-8: "... The register has to be read-cleared to enable further error address captures. ..."

* For register RAMPERRADDR, page 316, Table 6-11: "...This register must be read-cleared to enable further error address captures. ..."

BUT for register RAMSERRADDR I cannot find the information that it must also be read cleared. But I assume that it must also be read-cleared in case a single-bit error was detected.

Is my assumption correct?

Thank you and regards,

Oliver.

over 11 years ago

0 Charles Tsai over 11 years ago

TI__Guru**** 191906 points

Hello Oliver,

In order to store the next single bit error address, the SERR error status bit in the RAMERRSTATUS register. This is described in the SERR bit feld. However, I just requested an update in the TRM for the RAMSERRADDR to emphasize this again.

0 Charles Tsai over 11 years ago in reply to Charles Tsai

TI__Guru**** 191906 points

Sorry my setence did not complete. I meant "In order to store the next single bit error address, the SERR error status bit in the RAMERRSTATUS register needs to be write-clear".

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TCRAM: Read-clear needed also for RAMSERRADDR?