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TCRAM: Is the description of RAMUERRADDR wrong?

oliver.gruendonner
Intellectual 830 points

Hi.

My question is regarding the TMS570LS3137.

In spnu499b.pdf, page 314, Table 6-8., Description of bit field "RAMUERRADDR.UNCORRECTABLE ERROR ADDRESS", are also the following two sentences stated:

  * Sentence 1: "This register captures the address for which there was an uncorrectable error or an address parity error. ...".

  * Sentence 2: "For a redundant address decode and compare logic error ...".

So in sentence 1 is referred to the safety feature which is described in spnu499b.pdf, page 307, chapter "6.3.2 Support for Cortex-R4F CPU's Address and Control Bus Parity Checking". BUT in sentence 2 is referred to the safety feature which is described in spnu499b.pdf, page 307, chapter "6.3.3 Redundant Address Decode". So this is not consistent. I assume that the statement "an address parity error" in sentence 1 is wrong, and should be replaced with the statement "a redundant address decode and compare logic error".

Is my assumption correct?

Thank you and regards,

Oliver.

  • 0
    Intellectual 830 points

    Just as a note: In Table 6-8 is TWO times the statement "address parity error" stated: In paragraph 1 and 2. And IMHO are both statements wrong.

  • 0
    TI__Guru**** 191886 points

    Hello Oliver,

      Sorry for the confusion. Your understanding is correct. The RAMUERRADDR register is only meant to capture the error address due to an uncorrectable ECC error detected by the CPU or the address due to the redundant address and compare logic error. For address parity error, the address is captured in the RAMPERRADDR register. I just requested an update to the TRM to clarify the RAMUERRADDR register.