stcSelfCheck() generates ESM Group 1 Bit 27 Error

Hi Pashan,

Is this issue similar and tied to the fact that running pbist4 errata before stcSelfCheck() ends up with this error ?

If so I would prefer to close this thread so that we can keep this in a single thread which you had already created for cpuSelfTest().

Let us know.

Hello Support,

This issue is a separate question because ESM Group 1 Bit 27 is SET even if we don't call errata_PBIST_4().

Please let me know whether stcSelfCheck() is supposed to generate ESM Group 1 Bit 27 Error or not irrespective of errata_PBIST_4() function call.

Thank you.
Regards
Pashan

Hello Pashan,

  I'm able make it to work with a modification to the errata_PBIST_4(). In the original function, it tries to apply errata workaround to the PBIST ROM and followed by STC ROM. If I reverse the order then it works.

Change from

if (ROM_count == 0U)  // Original

to

if (ROM_count == 1U)  // New

Please try it and see if it works at your side. In the meantime I will contact our HalcoGen team to understand the reason and make necessary change.

Hello Charles,

            /* SELECT ROM */
            if (ROM_count == 0U)
            {
                /* SELECT PBIST ROM */
                *(volatile uint32 *)0xFFFFE520U = 0x00000002U;
                *(volatile uint32 *)0xFFFFE524U = 0x00000000U;
                pbistREG->RAMT                  = 0x01002008U;     /* RGS=1, RDS=0 -- PBIST_ROM */
            }
            else
            {
                /* SELECT STC ROM */
                *(volatile uint32 *)0xFFFFE520U = 0xFFF0007CU;
                *(volatile uint32 *)0xFFFFE524U = 0x06B3FFFFU;
                pbistREG->RAMT                  = 0x02002008U;   /* RGS=2, RDS=0 -- STC_ROM */
            }

I have attached the original code of Halcogen before your change, which I think correct if you look at the COMMENT I added.

If I swap the logic as you mentioned, then it will not select the correct ROM according to the RGS/RDS Table.
Original code is selecting the correct ROM according to RAMT register setting.

Please help me understand.
I think by swapping the original logic, you are indirectly not running the original errata_PBIST_4().

Let me know if I am wrong.
Thank you.
Regards
Pashan

Hello Charles,

It works once I change the order as you mentioned.

What about stcSelfCheck() function? I am getting ESM Group 1 Bit 27 SET for this function.
Is it supposed to set ESM Group 1 Bit 27 error?

cpuSelfCheck() function is now working without ESM Error.

Please let me know.
Thank you for your quick help.
Regards
Pashan

Hello Pashan,

I'm not too sure If I understand the problem. The only thing I change is highlighted below. The first time the ROM_count is 0 then it will first take the else clause which means it will select the STC ROM which is still RAM group 2. The next time when ROM_count is 1 then it will select the PBIST ROM.  

            /* SELECT ROM */
            if (ROM_count == 1U)
            {
                /* SELECT PBIST ROM */
                *(volatile uint32 *)0xFFFFE520U = 0x00000002U;
                *(volatile uint32 *)0xFFFFE524U = 0x00000000U;
                pbistREG->RAMT                  = 0x01002008U;                 }
            else
            {
                /* SELECT STC ROM */
                *(volatile uint32 *)0xFFFFE520U = 0xFFF0007CU;
                *(volatile uint32 *)0xFFFFE524U = 0x06B3FFFFU;
                pbistREG->RAMT                  = 0x02002008U;               }

Actually I even tried below and it also works. This simply makes it running the PBIST ROM two times.

 if (ROM_count == 0U) || ROM_count == 2U) /* note that in the upper for loop you need to change to ROM_count < 3U */

            {
                /* SELECT PBIST ROM */
                *(volatile uint32 *)0xFFFFE520U = 0x00000002U;
                *(volatile uint32 *)0xFFFFE524U = 0x00000000U;
                pbistREG->RAMT                  = 0x01002008U;                 }
            else
            {
                /* SELECT STC ROM */
                *(volatile uint32 *)0xFFFFE520U = 0xFFF0007CU;
                *(volatile uint32 *)0xFFFFE524U = 0x06B3FFFFU;
                pbistREG->RAMT                  = 0x02002008U;               }

Hello Pashan,

  It looks like your reply and my reply crossed. I will look at the cpuSelfCheck(). Since you have two posts on the same topic, can you please close the other one?

Hello Pashan,

  I'm not able to see the stcSlefCheck() fail with the ESM GP1.27 asserted whether or not the errata_PBIST_4 (with  the new modifcation that we talked about) is called first. Which version of HalCoGen do you use to generate the stcSelfCheck() function?

Hello Charles,

I am using 3.08 Halcogen Code.

Did you block the call to esmInit() function? Because that function clears ESM Group 1 Error.
May be pause before that esmInit() function and you should see the ESM Group 1 Error.
Let me know if you don't see the fault at your end.
Thank you.
Regards
Pashan

Hello Pashan,

  I use 3.08.01. Below is the function from 3.08.01. Can you send me the stcSelfCheck() function from 03.08 since it will take me some time to revert back to an older version.

void stcSelfCheck(void)

{

/* USER CODE BEGIN (8) */

/* USER CODE END */

volatile uint32 i = 0U;

/* Run a diagnostic check on the CPU self-test controller */

/* First set up the STC clock divider as STC is only supported up to 90MHz */

/* STC clock is now normal mode CPU clock frequency/2 = 180MHz/2 */

systemREG2->STCCLKDIV = 0x01000000U;

/* Select one test interval, restart self-test next time, 0x00010001 */

stcREG->STCGCR0 = 0x00010001U;

/* Enable comparator self-check and stuck-at-0 fault insertion in CPU, 0x1A */

stcREG->STCSCSCR = 0x1AU;

/* Maximum time-out period */

stcREG->STCTPR = 0xFFFFFFFFU;

/* wait for 16 VBUS clock cycles at least, based on HCLK to VCLK ratio */

/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */

/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */

for (i=0U; i<(16U + (16U * 1U)); i++){ /* Wait */ }

/* Enable self-test */

stcREG->STCGCR1 = 0xAU;

/* USER CODE BEGIN (9) */

/* USER CODE END */

/* Idle the CPU so that the self-test can start */

_gotoCPUIdle_();

/* USER CODE BEGIN (10) */

/* USER CODE END */

}

Hello Charles,

I have attached the file in mail.
Please see the mail.
Thank you.
Regards
Pashan