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ESM: Several questions regarding ESM group 2, channel 16.

oliver.gruendonner
Intellectual 830 points

Hi.

My questions are regarding the TMS570LS3137.

In spns162b.pdf, page 98, is stated "TCM - ECC live lock detect, Group2, 16". Since there is the name TCM inside I assume that this has something to do with ATCM, B0TCM, and B1TCM (i.e. it has something to do with flash and RAM).

I also found how this error could occur (in http://e2e.ti.com/support/microcontrollers/hercules/f/312/p/229014/804427.aspx#804427): "... when there are too many back-to-back single bit errors. ..."

In the Cortex-R4 and Cortex-R4F, Revision: r1p3, Technical Reference Manual, I found a short line on page 168: "[35] Processor livelock because of hard errors or exception at exception vector.a - 0x62". And this leads me to page 201, chapter "8.2.4 Hard errors".

So I have the following questions:

Question 1: Is it correct that Group 2, channel 16, can occur cause of a hard error either in flash (ATCM) or RAM (B0TCM, B1TCM)?

In http://e2e.ti.com/support/microcontrollers/hercules/f/312/p/332475/1162630.aspx#1162630 (which is regarding the flash) is stated at the end of the posting

"... As you may know that once the flash wrapper captures an ECC error events it will freeze its flags and addresses until the address registers is read. In order to capture subsequent new ECC errors you must clear the flags and read the address. Therefore, it is important in your ECC error handler routine to do so."

Question 2: Which is the corresponding status flag which will be set in case an ECC live lock error occurs? I.e. where it is described in spnu499b.pdf (cause I cannot find it)?

Question 3: Which is the corresponding address register, were the error address will be captured in case an ECC live lock error occurs? I.e. where it is described in spnu499b.pdf (cause I cannot find it)?

Question 4: Is it possible to test this live lock error mechanism?

Thank you and regards

Oliver.

  • 0
    TI__Guru**** 191486 points

    Hello Oliver,

     My answers are inline.

    Question 1: Is it correct that Group 2, channel 16, can occur cause of a hard error either in flash (ATCM) or RAM (B0TCM, B1TCM)?

    CT >> Yes, GP2.16 applies to ATCM and B0TCM and B1TCM.

    In http://e2e.ti.com/support/microcontrollers/hercules/f/312/p/332475/1162630.aspx#1162630 (which is regarding the flash) is stated at the end of the posting

    "... As you may know that once the flash wrapper captures an ECC error events it will freeze its flags and addresses until the address registers is read. In order to capture subsequent new ECC errors you must clear the flags and read the address. Therefore, it is important in your ECC error handler routine to do so."

    Question 2: Which is the corresponding status flag which will be set in case an ECC live lock error occurs? I.e. where it is described in spnu499b.pdf (cause I cannot find it)?

    CT>> There is no such status flag other than the livelock event generated out of the CPU and directly connected to the ESM.

    Question 3: Which is the corresponding address register, were the error address will be captured in case an ECC live lock error occurs? I.e. where it is described in spnu499b.pdf (cause I cannot find it)?

    CT>> Again, there is no address register for this.

    Question 4: Is it possible to test this live lock error mechanism?         

    CT>> The CPU will retry to read from the TCM memory if it detects a 1-bit error. Normally, this hard error can only happen if the memory has permanent fault. So this is hard to test. I think you can try to create an undefine instruction at the undefined exception vector. 

                                                             

  • 0 in reply to Charles Tsai
    Guru 13625 points

    Hi, Charles

    I have question about the following.

    Charles Tsai said:
    CT>> The CPU will retry to read from the TCM memory if it detects a 1-bit error. Normally, this hard error can only happen if the memory has permanent fault. So this is hard to test. I think you can try to create an undefine instruction at the undefined exception vector. 

    Now, I tried to create an undefine instruction, and was able to confirm that "TCM - ECC live lock detect flag" of ESM is set.

    Please teach me about this mechanism.

    Why is this flag is set?

    Best regards,

    FSSer

  • 0 in reply to Sh.Sasaki
    TI__Guru**** 191486 points
    Hello FSSer,
    Livelock is a state in which the processor pipeline is advancing and executing instructions, but the processor is repeatedly executes the same instruction so that it makes no progress through the program. When you have an underfined instruction at the undefined exception vector at 0x04 the processor can never advance the program flow and hence raises the livelock event. When ESM receives the livelock event, it is able to create an asynchronous exception (e.g. a NMI interrupt) to the processor in a normal way.
  • 0 in reply to Charles Tsai
    Guru 13625 points

    Hi Charles,

    Thanks to you, I understood this mechanism.

    I was clicking the "Like button", because "Verify Answer button" does not appear.

    Best regards,

    FSSer