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What is correct initialization for QEI0 on Launchpad TM4C123G?

I have not been able to get the QEI0 on a LaunchPad TM4C123G working correctly.  I am using  CCS 5.1 and Tivaware 2.1.  The hardware seems to correctly produce the QEI pulses.  There is no index pulse.

I probably have the initialization sequence wrong, as this is my first use of the QEI, but just do not see the issue. I have other GPIO's and I2C working.  Posted below is the code snippet for the QEI0 initialization followed by the snippet in a forever loop in a task where I read the QEI0 value.

Previous initialization, not posted here, enables all GPIO peripherals. followed by some portc & portf initialization.

I have reviewed the Lock/unlock requirements for Port D7 (NMI), read the other posts in the forum, but am not at all confident that I correctly understand the Lock/Unlock procedure.

The values returned by the QEIPositionGet() alternate between 2 values.  These are the initialized value, which is 1234 in the code snippet, and 1233.

All help will be appreciated.

Randy

*********************************************************************************

void QEI0_Init (void)
{
    // qei init
    // *******************************************************************************
    //    Initialize QEI (Quadrature Encoder Interface).
    //    Use GPIO Port D bits PD6 & PD7 There is no Index.
    //    Port D pin 7 defaults to a NMI input at reset. That functionality
    //       must be "unlocked" before it can be made available to QEI0.
    // *******************************************************************************

    // PD7
    // PD7 requires unlocking before configuration
    HWREG                 (GPIO_PORTD_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY; // unlocks port
    HWREG                (GPIO_PORTD_BASE + GPIO_O_CR) = GPIO_LOCK_UNLOCKED;  // enables Commit register

    // Enable Port D module
    SysCtlPeripheralEnable (SYSCTL_PERIPH_GPIOD);
    SysCtlPeripheralEnable (SYSCTL_PERIPH_QEI0);

    // PD6
    GPIOPinConfigure     (GPIO_PD6_PHA0);
    GPIOPinTypeQEI         (GPIO_PORTD_BASE, GPIO_PIN_6);

    GPIOPinConfigure     (GPIO_PD7_PHB0);
    GPIOPinTypeQEI         (GPIO_PORTD_BASE, GPIO_PIN_7);

    // re-lock PD7
    HWREG                 (GPIO_PORTD_BASE + GPIO_O_LOCK) = GPIO_LOCK_M; // lock register

    QEIConfigure        (QEI0_BASE,
        (QEI_CONFIG_CAPTURE_A | QEI_CONFIG_NO_RESET | QEI_CONFIG_QUADRATURE | QEI_CONFIG_NO_SWAP),
        100);

    QEIEnable (QEI0_BASE);

    // Zero the position counter
    QEIPositionSet (QEI0_BASE, 1234);
}  // QEI0_Init()

********************************************************************

    for (;;)
    {
        // Read the encoder position.
        qei_position1 = QEIPositionGet(QEI0_BASE);
.

.

  • Hi Randy,

    Randy Bulloch said:
    HWREG                (GPIO_PORTD_BASE + GPIO_O_CR) = GPIO_LOCK_UNLOCKED;  // enables Commit register

    GPIO_PORTD_BASE + GPIO_O_CR) = GPIO_LOCK_UNLOCKED //GPIO_LOCK_UNLOCKED value is 0x00000000

    should be as below.

    HWREG(GPIO_PORTD_BASE + GPIO_O_CR) |= 0x80; //PD7

    See, details below at GPIOCR from your device datasheet.

    Register 20: GPIO Commit (GPIOCR), offset 0x524
    "The GPIOCR register is the commit register. The value of the GPIOCR register determines which
    bits of the GPIOAFSEL, GPIOPUR, GPIOPDR, and GPIODEN registers are committed when a
    write to these registers is performed. If a bit in the GPIOCR register is cleared, the data being written
    to the corresponding bit in the GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN registers cannot
    be committed and retains its previous value. If a bit in the GPIOCR register is set, the data being
    written to the corresponding bit of the GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN registers
    is committed to the register and reflects the new value."

    -kel

  • Thanks for the "Verify Answer". I have not check further if your QEI code is okay. It is relax time where I am.

    Randy Bulloch said:
    HWREG                 (GPIO_PORTD_BASE + GPIO_O_LOCK) = GPIO_LOCK_M; // lock register

    Regarding this, just to refresh your memory that  "writing any other value to the GPIOLOCK register re-enables the locked state"

    -kel