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EPI pin level during power up configuration

Prad1
Genius 3825 points

Hi,

Our customer is using LM3S5791 and now planning to replace it with TM4C1294x device.
Can we assume the EPI peripheral is exactly the same to Stellaris's EPI?
(We shall do the test as soon as we get the TM4C1294x boards.)

As mentioned in the below post,we had an issue during EPI Peripheral configuration(startup),
all the hardware control pins "BSEL0n,BSEL1n,CS0 etc" level goes LOW(for a small duration)
http://e2e.ti.com/support/microcontrollers/stellaris_arm/f/471/t/324479.aspx

We have found that the EPI ports goes LOW when the below HB16 EPI configuration is executed.
EPIModeSet(EPI0_BASE, EPI_MODE_HB16)

We would like to confirm if this behaviour is same in TM4C1294x EPI and is according to the spec?


Regards
Prad

  • 0
    TI__Guru**** 244400 points

    Hello Prad

    The EPI Controller on TM4C129x has changes from LM3S. I have not so far seen an issue like this being reported on EPI for TM4C129x. My suggestion would be to enable the Pull Up on the IO's before setting the mode of EPI.

    Regards

    Amit

  • 0 in reply to Amit Ashara
    Genius 3825 points

    Hi Amit,

    Thank you so much for the quick reply.

    Actually we are using external pull up on these EPI pins.

    According to the Datasheet (both TM4C129x and LM3S),
    We believe this behaviour is according to the datasheet spec.
    Could you please let me know if the below understanding is true?

    -----------------------------
    In case of Host-bus 16-bit interface (standard SRAM) or SDRAM.
    the Control, address, and data pins are configured using the EPIHB16CFG and EPIHB16CFG2 registers.
    (from datasheet-SPMS433 page-852)

    But in order to configure EPI in HB16 mode, 0x3 should be written to the
    MODE bit in the EPI Configuration (EPICFG) register.

    And it is also mentioned that "Any write to the EPICFG register resets the register
    contents at offsets 0x010 and 0x014"

    Which means,
    0x010=EPIHB16CFG="0x00"
    0x014=EPIHB16CFG2="0x00"

    Which in turn resets(LOW level) the control, address and data pins of EPI.
    -----------------------------

    Best Regards
    Prad

  • 0 in reply to Prad1
    TI__Guru**** 244400 points

    Hello Prad,

    Yes, that is correct. It would glitch for one-clock cycle. In case of SDRAM the CS,WEn will go low but the CKE will remain low, till SDRAMCFG is not setup. In effect it will not cause the SDRAM memory to misbehave.

    Regards

    Amit

  • 0 in reply to Amit Ashara
    Genius 3825 points

    Hi Amit,

    Thank you for the confirmation.
    In our case we are using the EPI in HB16 mode.
    And the EPI is connected to SRAM and Flash.

    Because of this glitch, every time when the power is applied or the device is reset,
    a "00" value is written unintentionally to the staring address of SRAM.

    We can solve this issue through software,
    but we wanted to confirm if this kind of behavior is normal and according to the spec.

    Best Regards
    Prad