Hi,
I'm having some issues understanding the I2C initialisation. I based my code on that generated by Halcogen but after finding it does not work I've looked into the code and I have a few questions.
Here is the Halcogen Code:
/** - i2c Enter reset */
i2cREG1->MDR = (uint32)((uint32)0U << 5U);
/** - i2c Out of reset */
i2cREG1->MDR = (uint32)I2C_RESET_OUT;
/** - set i2c mode */
i2cREG1->MDR = (uint32)((uint32)0U << 15U) /* nack mode */
| (uint32)((uint32)0U << 14U) /* free running */
| (uint32)(0U) /* start condition - master only */
| (uint32)((uint32)0U <<11U) /* stop condition */
| (uint32)((uint32)1U <<10U) /* Master/Slave mode */
| (uint32)((uint32)I2C_TRANSMITTER) /* Transmitter/receiver */
| (uint32)((uint32)I2C_7BIT_AMODE) /* xpanded address */
| (uint32)((uint32)0U << 7U) /* repeat mode */
| (uint32)((uint32)0U << 6U) /* digital loop back */
| (uint32)(I2C_RESET_OUT) /* Bring Out of Reset */
| (uint32)((uint32)0U << 4U) /* start byte - master only */
| (uint32)(1U) /* free data format */
| (uint32)(I2C_8_BIT); /* bit count */
This code disagrees with the TRM in a number of ways.
1.
TRM states "IRS must be 0 while the I2C module is being configured."
However Halcogen has IRS = 1 during configuration.
2.
TRM has FDF as bit 3
Halcogen has FDF as bit 0
Outside of this i have a few more questions
3.
When FDF is used please confirm that the I2C module does not need to have any data written within the I2CSAR or I2CCNT registers, as I understand it they would not contain useful information.
Cheers
Alan