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Tiva C timerIntEnable FaultISR

Hello, 

I'm using TM4C123G launchpad. Im reading the adxl345 through timer. And some times my code stack on Faultisr. So i examine the registers using Diagnosing Software Faults in Stellaris instructions and i found that 

TimerIntEnable:
000015ca: 6982 LDR R2, [R0, #24]  This instruction is causing problem.
000015cc: 4311 ORRS R1, R2
000015ce: 6181 STR R1, [R0, #24]
000015d0: 4770 BX R14

MSP reg is pointing on this part of memory

40030000 00000001 00000000 00002000
0BEBC200 00000819 000015CA 61000012

So it looks like because of this part of code, program sometimes stucks.

void IntGPIOc(void){
ADXL345_READ(ADXL345_INT_SOURCE_REG, &int_source); //read status register for interrupt
GPIOIntClear(GPIO_PORTC_BASE, GPIO_PIN_4|GPIO_PIN_5);
ADXL345_READ(ADXL345_ACT_TAP_STATUS_REG, &test_1); // read act status to find which axis sensed activity
ADXL345_READ(ADXL345_FIFO_STATUS, &test_1); // read fifo status
GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_2, GPIO_PIN_2);

l=1;

// if part is in active mode turn of timer1 and turn on timer0

if (int_source&0x10){ 
TimerIntDisable(TIMER1_BASE,TIMER_TIMA_TIMEOUT);
GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_2, 0);
GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_3, 0);
TimerIntEnable(TIMER0_BASE,TIMER_TIMA_TIMEOUT);

}

// if part is in sleep mode turn of timer0 and turn on timer1
if (int_source&0x08){TimerIntDisable(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
TimerIntEnable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);
GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_2, 0);
}
if (int_source&0x04){
interr=1;}
if (int_source&64){tap=2; }
if (int_source&32){tap=3; }

}

Here is my config

void TimerA_configure_for_ADXL345(void){
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0);
TimerConfigure(TIMER0_BASE,TIMER_CFG_A_PERIODIC);
ROM_TimerLoadSet(TIMER0_BASE, TIMER_A, ROM_SysCtlClockGet()/140);
IntEnable(INT_TIMER0A);
ROM_TimerIntEnable(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
ROM_TimerEnable(TIMER0_BASE, TIMER_A);

}
void TimerA1_config_for_ADXL345(unsigned long ulFrequency){
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);
ROM_TimerConfigure(TIMER1_BASE,TIMER_CFG_A_PERIODIC);
ROM_TimerLoadSet(TIMER1_BASE, TIMER_A, ROM_SysCtlClockGet()/ulFrequency);
ROM_IntEnable(INT_TIMER1A);
ROM_TimerEnable(TIMER1_BASE, TIMER_A);

}
void GPIO_INT_PIN_CONF(void){
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_4, GPIO_DIR_MODE_IN);
GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_5, GPIO_DIR_MODE_IN);
GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_4, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPD);
GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_5, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPD);
GPIOIntTypeSet(GPIO_PORTC_BASE, GPIO_PIN_4, GPIO_HIGH_LEVEL);
GPIOIntTypeSet(GPIO_PORTC_BASE, GPIO_PIN_5, GPIO_HIGH_LEVEL);
GPIOIntEnable(GPIO_PORTC_BASE, GPIO_PIN_4);
GPIOIntEnable(GPIO_PORTC_BASE, GPIO_PIN_5);
IntEnable(INT_GPIOC);
}

Can you tell me what is wrong with config? 

  • Hello Matthew,

    It looks like that the CPU got a bus fault when TIMER_ICR for Timer-0 register was being accessed. You can check the Fault Address in NVIC_FAULTADDR and it should be a precise fault as given in NVIC_FAULTSTAT register.

    At the time of the Fault please do check if the RCGC register for timer in SYSCTL is set.

    Regards

    Amit