I'm having trouble implementing a simple 64-bit counter in N2HET. The CNT and WCAP functions work fine, but the instructions below do not. My init sets HETCGR = 0x30001 (IS=1, CMS=1, TO=1), HETPFR=0x600, and HETPCR=5 (parity disabled). I've manually reviewed my #defines and they appear to match the values in the reference manual, but here's what I see:
- Problem #1: instruction[0] is supposed to put a 1 in register T, but instruction[1] always shows register T to be zero. (I capture register T correctly when I run a CNT operation on it, so I know the WCAP works).
- Problem #2: instruction[2] doesn't change IMM data. (e.g. even when I'm running a counter in the T register)
- Problem #3: I expect instructions[0] and [1] to execute only once, but they seem to be running continously (based on HETADDR, which is always in the range [0..3] but usually reads zero on my emulator).
- Problem #4: HETPAR = 4, but parity is disabled and I haven't written to that memory (this may be expected behavior; the emulator reads back HET RAM which I have not initialized)
I assume I'm doing something dumb, but can't figure it out. Hope you can advise...
Thanks in advance,
Bill Naro
// SOURCE CODE FOR HET INSTRUCTION TABLE DEFNIITION:
static const PSP_TIME_HET_Instruction_T HET_64BIT_COUNTER_C[] = { // initialization instructions // [0] : put 1 in register T, advance to next step { (PGM_ALU_D | PGM_NEXT_M(1u)), // 0x2800 (CTL_ALU_D | SUBOPCODE_ADD_D | SRC1_IMM_D | SRC2_ZERO_D | DEST_T_D), // 0x880024 0x00000001u, 0x00000000u }, // [1] : capture register T (just to verify it was initialized properly), advance to next step { (PGM_WCAP_D | PGM_NEXT_M(2u)), // 0x5600 (DEST_T_D), // 0x4 0x00000000u, 0x00000000u }, // operation instructions - trying to run just these two instructions continuously... // [2] : increment 64-bit counter LSW by adding register T, advance to next step [3] { (PGM_ALU_D | PGM_NEXT_M(3u)), // 0x6800 (CTL_ALU_D | SUBOPCODE_ADD_D | SRC1_IMM_D | SRC2_T_D | DEST_IMM_D), // 0x8E00A4 0x00000000u, 0x00000000u }, // [3] : increment 64-bit counter MSW on LSW rollover by adding carry, jump back to previous step [2] { (PGM_ALU_D | PGM_NEXT_M(2u)), // 0x4800 (CTL_ALU_D | SUBOPCODE_ADC_D | SRC1_IMM_D | SRC2_ZERO_D | DEST_IMM_D), // 0x18800A4 0x00000000u, 0x00000000u }, };