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One or more sections of your program falls into a memory region that is not writable

Other Parts Discussed in Thread: TMDSRM48HDK, RM48L952, SEGGER, HALCOGEN

While using latest CCS and TMDSRM48HDK evaluation board with processor RM48L952 I get the error "One or more sections of your program falls into a memory region that is not writable" when starting a debug session.  I am not able to reprogram the flash or erase the flash once this occurs (using the onboard TI XDS100v2 USB Emulator).  Though the processor is correctly running my last loaded build and I am able to step through the code without issue.  The processor and flash seems perfectly operable.

A coworker brought in a Segger J-Link debugger.  Using the Segger debugger we were able to erase the flash on the board.  After this, the XDS100v2 using CCS was able to reprogram the board.  We could continually reprogram the board as long as we did not terminate the current debug session.  If the current session is terminated, the programming problem re-appears and persists.

Next, we left the Segger debugger plugged in.  We also would get the error if we tried to program the flash using the segger when using CCS.  But, if we commanded a cpu reset using the J-Link software ("r" in J-Link Commander), CCS was then able to reprogram the flash.  One of the last things I was trying before this problem occured was I was trying to get the dhrystone DMIPS number that is published and I was running the HCLK at 220MHz.

I changed the halcogen settings to put the HCLK at 200MHz, halted the cpu using the segger debugger and reprogrammed the part.  I then connected the XDS100v2 and the problem no longer occured.

What is also interesting is the Segger is able to do a hardware reset of the CPU using CCS using the reset option, but the XDS100v2 will not.  When a segger is connected, the error can be avoided by doing a CPU reset and then doing a Debug load.  This will not work if the XDS100v2 is in use.

It appears the solution for this issue, is for CCS to command a true cpu hardware reset and hold processor in reset (if possible) to force the CPU to be in a state that the XDS100v2 can then reprogram the flash.

The workaround is to not set the HCLK above 200MHz to avoid problems with programming with CCS and the XDS100v2.

I hope this information helps others out that have struggled with this issue.  I'll look forward to see if there is a CCS change in the future to resolve this issue.  If you haven't thrown away an old board that you thought was inoperable due to this issue, it's very likely you can resurrect it using the info above.

Thank you,

Matt