Hello,
I am having trouble getting a timer to run in one-shot mode with the action mode configured to immediately clear the CCP pin and then set the pin on time-out of the timer.
Here is the code where I initialize the timer:
/**
* Initializes Timers for one shot operation of the LDAC pulse
*
* \param enForcer - enables the LDAC_FORCER timer
* \param enQuad - enables the LDAC_QUAD timer
* \param pulseWidth - Number of clock cycles to pulse the LDAC signal low.
*
* \note Not available on the GTBE-TM4C123GXL
**/
void DAC_initTimersLDAC(bool enForcer, bool enQuad, uint32_t pulseWidth) {
// LDAC_FORCER Timer
MAP_SysCtlPeripheralEnable(DAC_LDAC_GPIO_PERIPH);
if(enForcer) {
MAP_GPIOPinTypeTimer(DAC_LDAC_GPIO_BASE, DAC_LDAC_FORCER_PIN);
MAP_GPIOPinConfigure(DAC_LDAC_FORCER_PIN_CONFIG);
MAP_SysCtlPeripheralEnable(DAC_LDAC_FORCER_TIMER_PERIPH);
MAP_TimerConfigure(DAC_LDAC_FORCER_TIMER_BASE, TIMER_CFG_SPLIT_PAIR | TIMER_CFG_B_ONE_SHOT | TIMER_CFG_B_ACT_CLRSETTO);
MAP_TimerLoadSet(DAC_LDAC_FORCER_TIMER_BASE, DAC_LDAC_FORCER_TIMER, pulseWidth);
}
// LDAC_QUAD Timer
if(enQuad) {
MAP_GPIOPinTypeTimer(DAC_LDAC_GPIO_BASE, DAC_LDAC_QUAD_PIN);
MAP_GPIOPinConfigure(DAC_LDAC_QUAD_PIN_CONFIG);
MAP_SysCtlPeripheralEnable(DAC_LDAC_QUAD_TIMER_PERIPH);
MAP_TimerConfigure(DAC_LDAC_QUAD_TIMER_BASE, TIMER_CFG_SPLIT_PAIR | TIMER_CFG_A_ONE_SHOT | TIMER_CFG_A_ACT_CLRSETTO);
MAP_TimerLoadSet(DAC_LDAC_QUAD_TIMER_BASE, pulseWidth, TIMER_A);
}
}
I then try and restart the timer within an EOT (end of transmission) interrupt generated by one of the SPI peripherals. Here is the interrupt:
/**
* Interrupt handler for loading the DACs with the timer after updating them
* \note Need to add the ISR to the NVIC table in the row labeled "SSIX Rx and Tx"
**/
void DAC_intHandlerSSItimer(void) {
//SSIIntClear(DAC_SSI_BASE, DAC_SSI_INT_TYPE)
HWREG(DAC_SSI_BASE + SSI_O_ICR) = DAC_SSI_INT_TYPE;
MAP_TimerLoadSet(DAC_LDAC_FORCER_TIMER_BASE, DAC_LDAC_FORCER_TIMER, 50);
//TimerEnable(DAC_LDAC_FORCER_TIMER_BASE, DAC_LDAC_FORCER_TIMER);
HWREG(DAC_LDAC_FORCER_TIMER_BASE + TIMER_O_CTL) |= DAC_LDAC_FORCER_TIMER & (TIMER_CTL_TAEN | TIMER_CTL_TBEN);
}
Here are some of the defines used:
// ~LDAC_FORCER and ~LDAC_Quad #define DAC_LDAC_GPIO_PERIPH SYSCTL_PERIPH_GPIOM #define DAC_LDAC_GPIO_BASE GPIO_PORTM_BASE #define DAC_LDAC_FORCER_PIN GPIO_PIN_1 #define DAC_LDAC_FORCER_PIN_CONFIG GPIO_PM1_T2CCP1 #define DAC_LDAC_FORCER_TIMER_PERIPH SYSCTL_PERIPH_TIMER2 #define DAC_LDAC_FORCER_TIMER_BASE TIMER2_BASE #define DAC_LDAC_FORCER_TIMER TIMER_B #define DAC_LDAC_QUAD_PIN GPIO_PIN_2 #define DAC_LDAC_QUAD_PIN_CONFIG GPIO_PM2_T3CCP0 #define DAC_LDAC_QUAD_TIMER_PERIPH SYSCTL_PERIPH_TIMER3 #define DAC_LDAC_QUAD_TIMER_BASE TIMER3_BASE #define DAC_LDAC_QUAD_TIMER TIMER_A
The problem is that when I measure the pin that should be outputing a low pulse while the timer is running I don't see anything at all, the pin just remains high. The CCP pin should be cleared when the timer starts and then set when the timer times out so that it is low while the timer is running.
I know the EOT interrupt is triggering for sure and the device supports the action modes as reported in the datasheet, so there must be some problem with the initialization that is called at the start of the main program or timer enabling code which is executed in the SSI EOT interrupt.
My full code is attached:
3302.GTBE_mainTestDRDYpllCMSIS - Timer Problem.zip
Regards,
Curtis
