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RE: C compilator and TMS570LS3137 bug DEVICE#B064

Prad1
Genius 3825 points
Other Parts Discussed in Thread: RM46L430

Hi Sunil,

Our customer is also using RM46L430 and are concerned about the "DEVICE#B064:" errata
and the STMxx instructions.

Could you please let me know if there are any updates about the compiler update.
Our customer is using IAR EWARM.

Best Regards
Prad.

  • 0
    TI__Guru 68920 points

    Prad,

    I split the thread becuase the other one was already verified answerd and adding on to it likely will result in the new question being missed.

    For IAR roadmaps - we can't really comment.  You'd need to check with IAR as to their development plans.   They are aware of the errata though.

  • 0 in reply to Anthony F. Seely
    Genius 3825 points

    Thank you Anthony,

  • 0 in reply to Prad1
    Genius 3825 points

    Hi Anthony,

    Just in case could you please let me
    if this errata has a workaround (Compiler update) in case of TI's CCS?

    Best Regards
    Prad

  • 0 in reply to Prad1
    TI__Guru 68920 points

    I believe it does but I'll loop in a colleague who has been working the issue w. the compiler team.

  • 0 in reply to Prad1
    TI__Mastermind 49120 points

    Hi Prad,

    Yes, the TI CodeGen Tools version 5.1.4 and later have the required workaround in place. I am pasting below from the release notes of CGT version 5.1.4

    ===============================================================================
4) Silicon Exception in Burst Write to External Memory
===============================================================================

To work around the silicon exception in burst write to external memory, you can use "--no_stm" option. It will translate a single STMXXX family instruction to a sequence of STR or VSTR instructions.

This option will also direct all calls to memset/memcpy to a different version (no_stm_memset/no_stm_memcpy) in the RTS library.

The option is a hidden option at this time and is not available for configuration using CCS. It needs to be manually added to the compilation script/command.

    In addition to the use of this "--no_stm" switch, the application must also ensure that the external memory is not configured to be of "normal" type using the MPU.

    As for CCS, you can "check for updates" and install the latest versions of the compiler tools for the Cortex-R4(F) based MCUs.


    Regards,
    Sunil
  • 0 in reply to Sunil Oak
    Genius 3825 points

    Hi Anthony, Sunil

    Thank you so much for the information.

    We have confirmend that this problem has workaround in CCS compiler,
    but unfortunately our customer's application is based on IAR and they are
    not able to switch to CCS at this juncture.
    In order to continue with the IAR, we need this errata to be solved in IAR also.

    Note: this errata is too much critical for our customer's application.

    We have requested Local IAR(Japan) to put an workaround in their compiler also,
    but we were told by the local IAR team that, the IAR Headquarters may not start working
    on a workaround just with a request from the local IAR team.

    They may need the feedback from TI also, could you please help us to convince
    IAR Headquaters to consider a workaround for this errata.
    If necessary I shall make the same request to you through TI Japan also.
    (I can mail you the customer's details also: my mail ID:pradeep_kumar@ktl-corp.co.jp)

    It would be helpful if you could inform IAR team about the necessity of workaround to this errata.
    I believe there may be few other customers who may have the same issue.

    Best Regards.
    Prad

  • 0 in reply to Prad1
    TI__Mastermind 49120 points

    Hi Prad,

    We are working with IAR to see if we can implement the suggested workaround in their compiler as well. As you suggested, this request has already come in from multiple customers.

    I hope to get back to you with some more information on this next week.

    Regards, Sunil