With SysTick configured to be clocked by PIOSC/4 and system clock driven by the PLL at 80MHz, it seems that a read to STCURRENT register returns an unexpected value, at least when followed by some writes to other SysTick registers. Adding a delay (in the form of an extra read) seems to fix the issue:
now = timer->STCURRENT;
timer->STCURRENT; /* delay (otherwise 'now' value is wrong: ~323000 instead of ~398000) */
timer->STRELOAD = newPeriodCounts;
timer->STCURRENT = 0;
The datasheet for TM4C123GH6PM does not mention anything about a necessary delay upon SysTick register access, except an (unrelated) comment that a system clock of at least 8MHz is needed to access STRELOAD on page 138. The idea to delay came from the fact that the SysTick device is effectively in a separate slower clock domain from the core which is clocked by the system clock. If it is indeed necessary to delay, could we please find out by how much and for which register accesses specifically (the current fix is just a guess)?
Details that shouldn't be relevant: This is inside a modified SYSBIOS with a custom driver module for the SysTick device. Clock and TimestampProvider modified to consume the ITimer interface directly instead of through hal.Timer so that they can use the SysTick module. It later turned out that there's already a driver for SysTick in ti.sysbios.family.arm.m3.Timer as pointed out here [1], but it's not currently unused.
[1] http://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/p/290322/1014038.aspx#1014038
