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RM46x Silicon Cortex-R4 realted Errata

Prad1
Genius 3825 points
Other Parts Discussed in Thread: RM46L430

Hi,

With regards to RM46L430 errata, there are few Cortex-R4 related problems
and we need some advice about "CORTEX-R4#46".

This errata mentions that "The operation to prefetch an instruction by MVA,
as defined in the ARMv6 architecture" a CP15 accesses may generate an UNDEFINED exception.
The instruction is "MCR p15,0,<Rt>,c7,c13,1 ; NOP".

We would like to know, in case of a practical application where exactly this
errata could effect?. We don't know how to find out if our application program is affected by this errata,
Do we have to explicitly write a assembly code(above) in order to see this error?

I tried to ask the same question on the ARM forum
but there was no reply only...
http://community.arm.com/message/18792#18792
So I am posting here hoping some advice from the TI support.


Best Regards.
Prad

  • 0
    TI__Guru 68920 points

    Prad,

    I'd say I'm 99.9% sure you won't run into this unwittingly because the compiler normally does not generate coprocessor instructions;  unless you've used an intrinsic.

    If you want to be 100% sure you can check w. the compiler vendor that you're working with - either IAR or you could post to the TI compiler forum if you're switching to CCS for reasons of the other errata we've been discussing.