• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 30 subscribers
  • Views 406 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570LS3137 flash bank width

Jiri Janacek
Genius 3315 points

Dear all,

I am a bit confused about the following sentences containing in the TRM spnu499b, chapter 5.1.2:

bw - Normal data space bank data width of a Flash bank. The bw is 128 bits (144 bits including the
error correction bits).
bwe - EEPROM emulation bank is 128 bit wide (144 bits including the error correction bits).

As far as I know the program memory (flash bank 0-1 in the mentioned device) is connected to CPU via 64 bit ATCM interface with 8 bit calculated ECC. Emulated EEPROM is connected via Level 2 interface of the same width as ATCM.

Also my attempts with TI flash API library have shown that data alignment is 64 bit. Have a look at pretty historical posts ;-)

So it seems the chapter 5.1.2 does contain improper values, right?

Thanks for your clerification in advance,

Best regards,

Jiri

  • 0
    TI__Mastermind 22375 points

    Jiri,

    The information in the TRM spnu499b, chapter 5.1.2 is correct.

    The Flash banks are 128bit + ECC. This is to improve performance when the Flash wrapper is reading the Flash bank. 
    Also, when the wrapper send the DATA to the ATCM, this is done as a 64bits + ECC. The next data is already buffered in the Flash wrapper and will need no wait-state to be send to the ATCM.

    The same concept is for EEPROM.