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generate single ecc error in flash

David Sabol
Genius 4850 points
Other Parts Discussed in Thread: HALCOGEN

I'm working with CCS 5.4 and the SafeTi-HSK (using the TMS570).

I'd like to generate single ecc errors in RAM and Flash, generate an ESM group 1 notification, and then run some of my code when the error occurs.

 

The flow I am following is this (for Flash):

- disable flash ECC (uses Halcogen generated _coreDisableFlashEcc_)

- flip one bit from memory address (function _genSingEccErr_ below)

- enable flash ECC (uses Halcogen generated _coreEnableFlashEcc_)

- read from the memory address that was modified (function _readMemForEccCheck_ below)

 

However, instead of generating an ESM group 1 channel 6 error as I would expect, I go into the vimParityErrorHandler with error channel 56.

 

Is there are simple, straightforward way to cause single ecc errors in RAM and Flash (and double errors as well) which can cause a ESM group 1 notification and run user code?

 

Thanks,
David

;-------------------------------------------------------------------------------
; Generate single ECC error

; Requirements:

    .def     _genSingEccErr_
    .asmfunc

_genSingEccErr_

        cps #13 ; Switch to supervisory mode
        mov r0, #0x00180000 ; Load address to a scratch register
        ldr r1, [r0] ; read in a memory location from location
        eor r1, r1, #1 ; invert bit 0
        str r1, [r0]; store value back into address

    .endasmfunc

    ;-------------------------------------------------------------------------------
; Read memory for ecc check

; Requirements:

    .def     _readMemForEccCheck_
    .asmfunc

_readMemForEccCheck_

        cps #13 ; Switch to supervisory mode
        mov r0, #0x00180000 ; Load address to a scratch register
        ldr r1, [r0] ; read in  memory location

    .endasmfunc

 

  • 0
    TI__Mastermind 22375 points

    David,

    If you are using Halcogen, there is a way to check for ECC on FLASH and RAM when you check the SAFETY INT/Enable Flash EXX check and Enable ESRAM ECC Check.

    Halcogen will generate the code to do single and double bit error. You can use this code as reference for your own routine.

  • 0
    TI__Mastermind 22375 points

    David,

    I looked more in details in your code and here are my comments:

    In _genSingEccErr_ you are doing:

    1]  cps #13 ; Switch to supervisory mode
    I assume you are in USER mode and want to gain privilege. This is not working. The CPSR can only be write accessed in privilege mode. The solution is to use a SWI instruction while in USER mode to gain privilege.

    2]       mov r0, #0x00180000 ; Load address to a scratch register
              ldr r1, [r0] ; read in a memory location from location
              eor r1, r1, #1 ; invert bit 0
              str r1, [r0]; store value back into address

    You cannot write to flash like you write to RAM. To write to FLASH, you have to first erase the sector and then re-write it with the new values. This is done using our FLASH API.

    You are also saying that your code generated a  vimParityErrorHandler.
    Does the VIM initialized before running you Flash or RAM ecc check?

    It will be easier if you can share your project (CCS and Halcogen) so I can have a look.