Generic question - Masked ROM for library routines and flash for application

Hello Tushar,

TIVA is a M4 device. There is no M0 device based TIVA part.

Regards

Amit

Hi Amit,

I am trying to get infomation regarding the following concept and it is not specific to any architecture (i.e. independent of core)

"Scenario - Masked ROM will be used for storing library routines and low level device driver. Flash memory will be used for application.  Flash memory will be around 4KB. Application will call library functions available into Masked ROM
Queries:
1. With respect to firmware, how the functions available into masked ROM will get linked to application available into flash.
2. If suppose I call function EEPROM_Read(Source_address, no. of bytes, destination_address) which is stored into masked ROM, how it gets linked?

I want to understand this concept of having library functions into Masked ROM and its usage into application flash.
Request you to share controller details with software / API user guide, which are using above techniques so that i can study it and understand its concept w.r.t. firmware development."

Thanks,
Tushar

Hello Tushar,

While your query is very generic, I would try to explain it as simplistically as possible.

The low level device driver are placed in ROM and have all the sub-function call and literals as well in ROM. The application code refers to these ROM functions and have to be mapped in a header file, which would contain a reference in the form of a pointer to a ROM location where the function is located.

In effect the application code would be containing branch statements to these ROM location and would work as a means to link these ROM functions into an application code.

Regards

Amit

Amit has gone out of his way to be helpful here - despite the "well" being, "bit poisoned" w/earlier MCU mention.

You did highlight 4KB as flash size - and that will certainly impact the extent & capability of your code & program capability.  Keep in mind that there is fairly significant, flash program overhead - even when simply calling functions based w/in ROM.  Thus - you will note that most ARM vendors produce MCUs w/flash sized @ 16KB and (far) above.

Decades past - our small firm was "stuck" w/5K of a non-ARM MCU - which had insufficient program storage capability.  And - as you suggest/question - our only hope was to employ eeprom as the program's primary "calling mechanism."  Now in theory this did work - we ran code which could not fit w/in a limited program space - but executing from eeprom was...s.......l.......o.......w.

With passage of time things have speeded - but a too small flash program size is something we'd seek to avoid...

I want to take this as a new thread and want to discuss more. Our team is at the initial phase of the CHIP design and I am supposed to support firmware for it. So I am trying to brainstorm on various design possibilities into chip.

Other design approach would be: Small footprint (size) of non volatile memory.
Compression of firmware and load it into non-volatile memory. Uncompressed it into volatile memory.
Any such device (chip) exist which describes above design approach. It would be helpful for me if you can share documents of Chip part of it for study. 

This is a rather large topic, there has been at least one book written about it.  There are really no general answers.  You will note that PLCs, tablets and laptops take different approaches to the same question.

It's not processor family specific and certainly not TI specific and as such this forum is probably not the best one for discussion.  I'd suggest comp.arch.embedded.  

Robert

Agree - and poster may fare bit better there by not (immediately) highlighting competitive part/site etc... 

Duplicate: http://e2e.ti.com/support/microcontrollers/stellaris_arm/f/471/t/343565.aspx

Andy Neil said:

Duplicate

Seemed - during your absence - not more than 1 or 2 such "duplicates" were caught/convicted...