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TMS570 Clock drift due to internal TMS components

Henry Abril1
Intellectual 485 points

Hi,

Currently I would like to configure the DCC modules to check that the configuration of the PLL dividers, multiplication factor, etc are correct.

e.g.:

The DCC Module 2 will compare the OSCIN & the VCLK clock sources:
 * Osc. Freq 16MHz
 * VCLK = 90MHz

DISREGARDING THE EXTERNAL OSCILLATOR TOLERANCES/DRIFT, etc

Could you please help me to clarify which is the maximum drift(under any condition) I could expect in the output frequency due to the internal stages of the TMS570 (PLL, divider, multipliers, etc)?

The DCC Module 2 will compare the OSCIN & the VCLK clock sources:
 * Osc. Freq 16MHz
 * VCLK = 90MHz
 * Allowed Clock Drift +/- ??%

Thank you and BR

 

  • 0
    TI__Mastermind 23000 points

    Hi Henry,

    I am not aware of any specification documenting clock drift for the MCU.  It is not a published datasheet parameter.  If this is a critical element to you I would recommend that you characterize behavior in your system using the ECLK to monitor the selected internal clocks which you deem as critical to your application.

    In practical application, the accuracy of the DCC will be limited by the accuracy of the external oscillator.

    Regards,

    Karl

  • 0 in reply to KGreb
    Intellectual 485 points

    Hi Karl,

    IMHO (please correct me if I am wrong) that value (if exists and there is an internal drift) could be critical for any user that wants to use the DCC module.

    Reason:

    Please take an example like this:

    OSCIN: max. drift under any condition 0.95%

    So the user calculates the DCC values for a max. clock drift of 1% expecting to be in range under ANY situation.

    What would happen if the  internal clock drift for the MCU stages are adding under certain circumstances more than 0.05% drift? --> DCC error detection.

    For that reason I kindly ask you if there is any chance to try to get that parameter internally in TI?

    Probably there is not any drift added due to the internal stages, but would be nice to know it, just to avoid future issues in our development.

    Thank you and BR.

    

    

    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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						in reply to Henry Abril1
					
									
    
	
    
	                                    
                      
    
                        
                          TI__Mastermind
                        23000 points
                      
    
                          
                   		
		
    
					
    Hello Henry,
    

    As previously noted, TI does not publish this value in any datasheet.  Because the behavior of the overall clocking system is heavily system dependent, DCC limits are typically characterized by the system integrator to reflect the behavior of their specific system.
    

    

    Regards,
    

    Karl
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                 	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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