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Can cpu registers be memory mapped?

Vineel Kumar Reddy Kovvuri
Prodigy 80 points

Hi All,

I am wondering why aren't cpu registers never memory mapped. I am new to embedded development, I knew that most of the peripherals registers are accessed via memory mapped IO. Is there any specific reason behind it? Please correct if my understand is incorrect.

Thanks

Vineel

  • 0
    TI__Guru**** 244400 points

    Hello Vineet,

    The CPU registers are like variables used by the CPU to hold. store and operate on data and compute address to execute a program. by memory mapping it how would it compute it's own address?

    Regards

    Amit

  • 0 in reply to Amit Ashara
    Guru 47900 points

    Along w/Amit's well chosen argument - should not the ARM designers have placed their key/critical Registers exactly as they've done? 

    Coupled so closely w/in the MCU - those Registers are not burdened with competing bus accesses or other operational requirements which may slow or otherwise impede normal/customary MCU operations.

    If such detail really is your interest - Joseph Yiu's book (re ARM Cortex M3) greatly details many of the more notable, "methods/madness" w/in ARM design/development...

  • 0 in reply to Amit Ashara
    Prodigy 80 points

    Hi Amit,

    I am wondering if there is a way for the privilege(OS) code can read the register values from a memory map not necessarily directly using instructions. For example assume if the register set is present at say 0x20000000 Is it incorrect in imagining a scenario where the program can read(ofcourse again using cpu instructions which refer to registers(variables)) register values from 0x20000000. please correct me if i am wrong. Could you please eloborate on what you mean by "how would it compute it's own address". Anyways thanks for the reply 

  • 0 in reply to Vineel Kumar Reddy Kovvuri
    Guru 47900 points

    @ Amit,

    Your brief foray into, "Socratic Method" appears to have landed you w/in tough (i.e. ongoing) spot, here. 

    Reference book read was my suggested, "side-step/escape"...)

  • 0 in reply to cb1
    Guru 26105 points

    Hi,

    In fact micro controllers where cpu registers are mapped really exists, i could give you 3-4 examples (a good one is 80C196 from Intel, made for 35 years long, now out of production: each ram location is a cpu register) - but this fact is related to a general architecture - while those falling into this category belongs mainly to von Newman concept, ARM/Cortex-Mx are built on Harward architecture - the main reason is the bottleneck on instruction/data bus, common in von Newman and separate in Harward. 

    Petrei

  • 0 in reply to Petrei
    TI__Guru**** 244400 points

    Thanks Petrei and cb1. Your experience and posts give directions to lot of us... Still catching up on external sites and suggested readings.

    Hello Vineet,

    To answer your specific question

    1. Let us take you want to add two variables in RAM and store the result in RAM. You would need two sets of addresses. One set for SRAM access and second set to access the register which is memory mapped. So you have computed the address of the SRAM variable using the register which is memory mapped. But how do you compute the address of the register and where is this address held for all the operations?

    2. What all peripherals have access to this memory mapped CPU register? The CPU is running the user code and no other peripheral needs to modify this space.

    Regards

    Amit

  • 0 in reply to Petrei
    Guru 27665 points

    The 80c96/80c196 family was the first that occured to me as well.  I enjoyed using it for a while myself (and took advantage of its (semi?) Harvard architecture features as well).  It's also one of the minority of architectures that uses three operands.  One of the advantages of this kind of architecture is that it can make context switches remarkably fast since you can set up at least some switches to not require saving and restoring the working register set. 

    Although the chip has been out of production for a while I do know of one company still building product with it.  It was (still is?) also available as an ASIC core.

    There is also a Spark architecture that maintains a large register set that uses a portion of for the working set and changes that portion during function calls moving any overflow to/from memory as desired.  The ST10/C166 Family from ST an (when I used them) Siemens performed a similar trick with the stack with a small on board stack that could spill out to main memory.

    Robert

  • 0 in reply to Amit Ashara
    Prodigy 80 points

    Thanks Amit, Petrei and cb1 for the replies.